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Commit 46b6b38e authored by Eric Kooistra's avatar Eric Kooistra
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Ported common FIFO IP from /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk...

Ported common FIFO IP from /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk to /home/kooistra/svnroot/UniBoard_FP7/RadioHDL/trunk and verified it with tb_common_fifo_dc_mixed_widths.vhd.
parent 39742b9f
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hdl_lib_name = common hdl_lib_name = common
hdl_library_clause_name = common_lib hdl_library_clause_name = common_lib
hdl_lib_uses = technology tech_memory tst hdl_lib_uses = technology tech_memory tech_fifo tst
build_sim_dir = $HDL_BUILD_DIR build_sim_dir = $HDL_BUILD_DIR
build_synth_dir = build_synth_dir =
...@@ -13,9 +13,6 @@ synth_files = ...@@ -13,9 +13,6 @@ synth_files =
$UNB/Firmware/modules/common/src/vhdl/common_lfsr_sequences_pkg.vhd $UNB/Firmware/modules/common/src/vhdl/common_lfsr_sequences_pkg.vhd
$UNB/Firmware/modules/common/src/vhdl/common_components_pkg.vhd $UNB/Firmware/modules/common/src/vhdl/common_components_pkg.vhd
$UNB/Firmware/modules/MegaWizard/fifo_sc/fifo_sc.vhd
$UNB/Firmware/modules/MegaWizard/fifo_dc/fifo_dc.vhd
$UNB/Firmware/modules/MegaWizard/fifo_dc/fifo_dc_mixed_widths.vhd
$UNB/Firmware/modules/MegaWizard/arith/lut_add_sub.vhd $UNB/Firmware/modules/MegaWizard/arith/lut_add_sub.vhd
$UNB/Firmware/modules/MegaWizard/arith/dsp_add_sub.vhd $UNB/Firmware/modules/MegaWizard/arith/dsp_add_sub.vhd
$UNB/Firmware/modules/MegaWizard/arith/dsp_mult_add2.vhd $UNB/Firmware/modules/MegaWizard/arith/dsp_mult_add2.vhd
...@@ -24,6 +21,11 @@ synth_files = ...@@ -24,6 +21,11 @@ synth_files =
$UNB/Firmware/modules/common/src/ip/MegaWizard/iobuf_in.vhd $UNB/Firmware/modules/common/src/ip/MegaWizard/iobuf_in.vhd
$UNB/Firmware/modules/common/src/vhdl/common_async.vhd
$UNB/Firmware/modules/common/src/vhdl/common_async_slv.vhd
$UNB/Firmware/modules/common/src/vhdl/common_areset.vhd
$UNB/Firmware/modules/common/src/vhdl/common_acapture.vhd
$UNB/Firmware/modules/common/src/vhdl/common_acapture_slv.vhd
$UNB/Firmware/modules/common/src/vhdl/common_pipeline.vhd $UNB/Firmware/modules/common/src/vhdl/common_pipeline.vhd
$UNB/Firmware/modules/common/src/vhdl/common_pipeline_sl.vhd $UNB/Firmware/modules/common/src/vhdl/common_pipeline_sl.vhd
$UNB/Firmware/modules/common/src/vhdl/common_pipeline_integer.vhd $UNB/Firmware/modules/common/src/vhdl/common_pipeline_integer.vhd
...@@ -39,6 +41,10 @@ synth_files = ...@@ -39,6 +41,10 @@ synth_files =
src/vhdl/common_ram_r_w.vhd src/vhdl/common_ram_r_w.vhd
src/vhdl/common_rom.vhd src/vhdl/common_rom.vhd
src/vhdl/common_fifo_sc.vhd
src/vhdl/common_fifo_dc.vhd
src/vhdl/common_fifo_dc_mixed_widths.vhd
$UNB/Firmware/modules/common/src/vhdl/common_wideband_data_scope.vhd $UNB/Firmware/modules/common/src/vhdl/common_wideband_data_scope.vhd
$UNB/Firmware/modules/common/src/vhdl/common_iobuf_in.vhd $UNB/Firmware/modules/common/src/vhdl/common_iobuf_in.vhd
$UNB/Firmware/modules/common/src/vhdl/common_iobuf_in_a_stratix4.vhd $UNB/Firmware/modules/common/src/vhdl/common_iobuf_in_a_stratix4.vhd
...@@ -47,11 +53,6 @@ synth_files = ...@@ -47,11 +53,6 @@ synth_files =
$UNB/Firmware/modules/common/src/vhdl/common_ddio_out.vhd $UNB/Firmware/modules/common/src/vhdl/common_ddio_out.vhd
$UNB/Firmware/modules/common/src/vhdl/common_ddio_out_a_stratix4.vhd $UNB/Firmware/modules/common/src/vhdl/common_ddio_out_a_stratix4.vhd
$UNB/Firmware/modules/common/src/vhdl/common_inout.vhd $UNB/Firmware/modules/common/src/vhdl/common_inout.vhd
$UNB/Firmware/modules/common/src/vhdl/common_async.vhd
$UNB/Firmware/modules/common/src/vhdl/common_async_slv.vhd
$UNB/Firmware/modules/common/src/vhdl/common_areset.vhd
$UNB/Firmware/modules/common/src/vhdl/common_acapture.vhd
$UNB/Firmware/modules/common/src/vhdl/common_acapture_slv.vhd
$UNB/Firmware/modules/common/src/vhdl/common_fanout.vhd $UNB/Firmware/modules/common/src/vhdl/common_fanout.vhd
$UNB/Firmware/modules/common/src/vhdl/common_fanout_tree.vhd $UNB/Firmware/modules/common/src/vhdl/common_fanout_tree.vhd
$UNB/Firmware/modules/common/src/vhdl/common_ddreg.vhd $UNB/Firmware/modules/common/src/vhdl/common_ddreg.vhd
...@@ -121,12 +122,6 @@ synth_files = ...@@ -121,12 +122,6 @@ synth_files =
$UNB/Firmware/modules/common/src/vhdl/common_rl_increase.vhd $UNB/Firmware/modules/common/src/vhdl/common_rl_increase.vhd
$UNB/Firmware/modules/common/src/vhdl/common_rl_register.vhd $UNB/Firmware/modules/common/src/vhdl/common_rl_register.vhd
$UNB/Firmware/modules/common/src/vhdl/common_fifo_rd.vhd $UNB/Firmware/modules/common/src/vhdl/common_fifo_rd.vhd
$UNB/Firmware/modules/common/src/vhdl/common_fifo_sc.vhd
$UNB/Firmware/modules/common/src/vhdl/common_fifo_sc_a_stratix4.vhd
$UNB/Firmware/modules/common/src/vhdl/common_fifo_dc_mixed_widths.vhd
$UNB/Firmware/modules/common/src/vhdl/common_fifo_dc_mixed_widths_a_stratix4.vhd
$UNB/Firmware/modules/common/src/vhdl/common_fifo_dc.vhd
$UNB/Firmware/modules/common/src/vhdl/common_fifo_dc_a_stratix4.vhd
$UNB/Firmware/modules/common/src/vhdl/common_blockreg.vhd $UNB/Firmware/modules/common/src/vhdl/common_blockreg.vhd
$UNB/Firmware/modules/common/src/vhdl/common_fifo_dc_lock_control.vhd $UNB/Firmware/modules/common/src/vhdl/common_fifo_dc_lock_control.vhd
$UNB/Firmware/modules/common/src/vhdl/common_mem_mux.vhd $UNB/Firmware/modules/common/src/vhdl/common_mem_mux.vhd
......
...@@ -21,12 +21,14 @@ ...@@ -21,12 +21,14 @@
-- Purpose: Dual clock FIFO -- Purpose: Dual clock FIFO
LIBRARY IEEE, common_lib; LIBRARY IEEE, technology_lib, tech_fifo_lib;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_1164.ALL;
USE common_lib.common_pkg.ALL; USE work.common_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL;
ENTITY common_fifo_dc IS ENTITY common_fifo_dc IS
GENERIC ( GENERIC (
g_technology : NATURAL := c_tech_select_default;
g_note_is_ful : BOOLEAN := TRUE; -- when TRUE report NOTE when FIFO goes full, fifo overflow is always reported as FAILURE g_note_is_ful : BOOLEAN := TRUE; -- when TRUE report NOTE when FIFO goes full, fifo overflow is always reported as FAILURE
g_fail_rd_emp : BOOLEAN := FALSE; -- when TRUE report FAILURE when read from an empty FIFO g_fail_rd_emp : BOOLEAN := FALSE; -- when TRUE report FAILURE when read from an empty FIFO
g_dat_w : NATURAL := 36; g_dat_w : NATURAL := 36;
...@@ -48,3 +50,91 @@ ENTITY common_fifo_dc IS ...@@ -48,3 +50,91 @@ ENTITY common_fifo_dc IS
); );
END common_fifo_dc; END common_fifo_dc;
ARCHITECTURE str of common_fifo_dc IS
CONSTANT c_nof_words : NATURAL := 2**ceil_log2(g_nof_words); -- ensure size is power of 2 for dual clock FIFO
SIGNAL wr_rst : STD_LOGIC;
SIGNAL wr_init : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL ful : STD_LOGIC;
SIGNAL emp : STD_LOGIC;
SIGNAL nxt_rd_val : STD_LOGIC;
BEGIN
-- Control logic copied from LOFAR common_fifo_dc(virtex4).vhd
-- Need to make sure the reset lasts at least 3 cycles (see fifo_generator_ug175.pdf)
-- Wait at least 4 cycles after reset release before allowing FIFO wr_en (see fifo_generator_ug175.pdf)
-- Use common_areset to:
-- . asynchronously detect rst even when the wr_clk is stopped
-- . synchronize release of rst to wr_clk domain
-- Using common_areset is equivalent to using common_async with same signal applied to rst and din.
u_wr_rst : ENTITY work.common_areset
GENERIC MAP (
g_rst_level => '1',
g_delay_len => 3
)
PORT MAP (
in_rst => rst,
clk => wr_clk,
out_rst => wr_rst
);
-- Delay wr_init to ensure that FIFO ful has gone low after reset release
u_wr_init : ENTITY work.common_areset
GENERIC MAP (
g_rst_level => '1',
g_delay_len => 4
)
PORT MAP (
in_rst => wr_rst,
clk => wr_clk,
out_rst => wr_init -- assume init has finished g_delay_len cycles after release of wr_rst
);
-- The FIFO under read and over write protection are kept enabled in the MegaWizard
wr_en <= wr_req AND NOT wr_init; -- check on NOT ful is not necessary when overflow_checking="ON" (Altera) or according to fifo_generator_ug175.pdf (Xilinx)
rd_en <= rd_req; -- check on NOT emp is not necessary when underflow_checking="ON" (Altera)
nxt_rd_val <= rd_req AND NOT emp; -- check on NOT emp is necessary for rd_val
wr_ful <= ful WHEN wr_init='0' ELSE '0';
rd_emp <= emp;
p_rd_clk : PROCESS(rd_clk)
BEGIN
IF rising_edge(rd_clk) THEN
rd_val <= nxt_rd_val;
END IF;
END PROCESS;
u_fifo : ENTITY tech_fifo_lib.tech_fifo_dc
GENERIC MAP (
g_technology => g_technology,
g_dat_w => g_dat_w,
g_nof_words => c_nof_words
)
PORT MAP (
aclr => wr_rst, -- MegaWizard fifo_dc seems to use aclr synchronous with wr_clk
data => wr_dat,
rdclk => rd_clk,
rdreq => rd_en,
wrclk => wr_clk,
wrreq => wr_en,
q => rd_dat,
rdempty => emp,
rdusedw => rdusedw,
wrfull => ful,
wrusedw => wrusedw
);
proc_common_fifo_asserts("common_fifo_dc", g_note_is_ful, g_fail_rd_emp, wr_rst, wr_clk, ful, wr_en, rd_clk, emp, rd_en);
END str;
...@@ -40,12 +40,14 @@ ...@@ -40,12 +40,14 @@
-- is not a power of 2 multiple of g_wr_dat_w. After that g_nof_words have -- is not a power of 2 multiple of g_wr_dat_w. After that g_nof_words have
-- been written to the FIFO the rdusedw will wrap and the output goes wrong. -- been written to the FIFO the rdusedw will wrap and the output goes wrong.
LIBRARY IEEE, common_lib; LIBRARY IEEE, technology_lib, tech_fifo_lib;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_1164.ALL;
USE common_lib.common_pkg.ALL; USE work.common_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL;
ENTITY common_fifo_dc_mixed_widths IS ENTITY common_fifo_dc_mixed_widths IS
GENERIC ( GENERIC (
g_technology : NATURAL := c_tech_select_default;
g_note_is_ful : BOOLEAN := TRUE; -- when TRUE report NOTE when FIFO goes full, fifo overflow is always reported as FAILURE g_note_is_ful : BOOLEAN := TRUE; -- when TRUE report NOTE when FIFO goes full, fifo overflow is always reported as FAILURE
g_fail_rd_emp : BOOLEAN := FALSE; -- when TRUE report FAILURE when read from an empty FIFO g_fail_rd_emp : BOOLEAN := FALSE; -- when TRUE report FAILURE when read from an empty FIFO
g_nof_words : NATURAL := c_bram_m9k_fifo_depth; -- FIFO size in nof wr_dat words g_nof_words : NATURAL := c_bram_m9k_fifo_depth; -- FIFO size in nof wr_dat words
...@@ -68,3 +70,91 @@ ENTITY common_fifo_dc_mixed_widths IS ...@@ -68,3 +70,91 @@ ENTITY common_fifo_dc_mixed_widths IS
); );
END common_fifo_dc_mixed_widths; END common_fifo_dc_mixed_widths;
ARCHITECTURE str of common_fifo_dc_mixed_widths IS
CONSTANT c_nof_words : NATURAL := 2**ceil_log2(g_nof_words); -- ensure size is power of 2 for dual clock FIFO
SIGNAL wr_rst : STD_LOGIC;
SIGNAL wr_init : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL ful : STD_LOGIC;
SIGNAL emp : STD_LOGIC;
SIGNAL nxt_rd_val : STD_LOGIC;
BEGIN
-- Control logic copied from LOFAR common_fifo_dc(virtex4).vhd
-- Need to make sure the reset lasts at least 3 cycles (see fifo_generator_ug175.pdf).
-- Wait at least 4 cycles after reset release before allowing FIFO wr_en (see fifo_generator_ug175.pdf)
-- Use common_areset to:
-- . asynchronously detect rst even when the wr_clk is stopped
-- . synchronize release of rst to wr_clk domain
-- Using common_areset is equivalent to using common_async with same signal applied to rst and din.
u_wr_rst : ENTITY work.common_areset
GENERIC MAP (
g_rst_level => '1',
g_delay_len => 3
)
PORT MAP (
in_rst => rst,
clk => wr_clk,
out_rst => wr_rst
);
-- Delay wr_init to ensure that FIFO ful has gone low after reset release
u_wr_init : ENTITY work.common_areset
GENERIC MAP (
g_rst_level => '1',
g_delay_len => 4
)
PORT MAP (
in_rst => wr_rst,
clk => wr_clk,
out_rst => wr_init -- assume init has finished g_delay_len cycles after release of wr_rst
);
-- The FIFO under read and over write protection are kept enabled in the MegaWizard
wr_en <= wr_req AND NOT wr_init; -- check on NOT ful is not necessary according to fifo_generator_ug175.pdf
rd_en <= rd_req; -- check on NOT emp is not necessary
nxt_rd_val <= rd_req AND NOT emp; -- check on NOT emp is necessary for rd_val
wr_ful <= ful;
rd_emp <= emp;
p_rd_clk : PROCESS(rd_clk)
BEGIN
IF rising_edge(rd_clk) THEN
rd_val <= nxt_rd_val;
END IF;
END PROCESS;
u_fifo : ENTITY tech_fifo_lib.tech_fifo_dc_mixed_widths
GENERIC MAP (
g_technology => g_technology,
g_nof_words => c_nof_words,
g_wrdat_w => g_wr_dat_w,
g_rddat_w => g_rd_dat_w
)
PORT MAP (
aclr => wr_rst, -- MegaWizard fifo_dc_mixed_widths seems to use aclr synchronous with wr_clk
data => wr_dat,
rdclk => rd_clk,
rdreq => rd_en,
wrclk => wr_clk,
wrreq => wr_en,
q => rd_dat,
rdempty => emp,
rdusedw => rdusedw,
wrfull => ful,
wrusedw => wrusedw
);
proc_common_fifo_asserts("common_fifo_dc_mixed_widths", g_note_is_ful, g_fail_rd_emp, wr_rst, wr_clk, ful, wr_en, rd_clk, emp, rd_en);
END str;
...@@ -21,12 +21,14 @@ ...@@ -21,12 +21,14 @@
-- Purpose: Single clock FIFO -- Purpose: Single clock FIFO
LIBRARY IEEE, common_lib; LIBRARY IEEE, technology_lib, tech_fifo_lib;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_1164.ALL;
USE common_lib.common_pkg.ALL; USE work.common_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL;
ENTITY common_fifo_sc IS ENTITY common_fifo_sc IS
GENERIC ( GENERIC (
g_technology : NATURAL := c_tech_select_default;
g_note_is_ful : BOOLEAN := TRUE; -- when TRUE report NOTE when FIFO goes full, fifo overflow is always reported as FAILURE g_note_is_ful : BOOLEAN := TRUE; -- when TRUE report NOTE when FIFO goes full, fifo overflow is always reported as FAILURE
g_fail_rd_emp : BOOLEAN := FALSE; -- when TRUE report FAILURE when read from an empty FIFO g_fail_rd_emp : BOOLEAN := FALSE; -- when TRUE report FAILURE when read from an empty FIFO
g_use_lut : BOOLEAN := FALSE; -- when TRUE then force using LUTs via Altera eab="OFF", g_use_lut : BOOLEAN := FALSE; -- when TRUE then force using LUTs via Altera eab="OFF",
...@@ -53,3 +55,123 @@ ENTITY common_fifo_sc IS ...@@ -53,3 +55,123 @@ ENTITY common_fifo_sc IS
); );
END common_fifo_sc; END common_fifo_sc;
ARCHITECTURE str OF common_fifo_sc IS
CONSTANT c_use_eab : STRING := sel_a_b(g_use_lut, "OFF", "ON"); -- when g_use_lut=TRUE then force using LUTs via Altera eab="OFF", else default to ram_block_type = "AUTO"
CONSTANT c_fifo_af_latency : NATURAL := 1; -- pipeline register wr_aful
CONSTANT c_fifo_af_margin : NATURAL := g_af_margin+c_fifo_af_latency; -- FIFO almost full level
SIGNAL fifo_rst : STD_LOGIC;
SIGNAL fifo_init : STD_LOGIC;
SIGNAL fifo_wr_en : STD_LOGIC;
SIGNAL nxt_fifo_wr_en : STD_LOGIC;
SIGNAL fifo_wr_dat : STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
SIGNAL nxt_fifo_wr_dat : STD_LOGIC_VECTOR(fifo_wr_dat'RANGE);
SIGNAL fifo_rd_en : STD_LOGIC;
SIGNAL fifo_full : STD_LOGIC;
SIGNAL fifo_empty : STD_LOGIC;
SIGNAL fifo_usedw : STD_LOGIC_VECTOR(usedw'RANGE);
SIGNAL nxt_wr_aful : STD_LOGIC;
SIGNAL nxt_rd_val : STD_LOGIC;
BEGIN
-- Control logic copied from common_fifo_sc(virtex4).vhd
gen_fifo_rst : IF g_reset=TRUE GENERATE
-- Make sure the reset lasts at least 3 cycles (see fifo_generator_ug175.pdf). This is necessary in case
-- the FIFO reset is also used functionally to flush it, so not only after power up.
u_fifo_rst : ENTITY work.common_areset
GENERIC MAP (
g_rst_level => '1',
g_delay_len => 4
)
PORT MAP (
in_rst => rst,
clk => clk,
out_rst => fifo_rst
);
END GENERATE;
no_fifo_rst : IF g_reset=FALSE GENERATE
fifo_rst <= rst;
END GENERATE;
gen_init : IF g_init=TRUE GENERATE
-- Wait at least 3 cycles after reset release before allowing fifo_wr_en (see fifo_generator_ug175.pdf)
u_fifo_init : ENTITY work.common_areset
GENERIC MAP (
g_rst_level => '1',
g_delay_len => 4
)
PORT MAP (
in_rst => fifo_rst,
clk => clk,
out_rst => fifo_init
);
p_init_reg : PROCESS(fifo_rst, clk)
BEGIN
IF fifo_rst='1' THEN
fifo_wr_en <= '0';
ELSIF rising_edge(clk) THEN
fifo_wr_dat <= nxt_fifo_wr_dat;
fifo_wr_en <= nxt_fifo_wr_en;
END IF;
END PROCESS;
nxt_fifo_wr_dat <= wr_dat;
nxt_fifo_wr_en <= wr_req AND NOT fifo_init; -- check on NOT full is not necessary according to fifo_generator_ug175.pdf
END GENERATE;
no_init : IF g_init=FALSE GENERATE
fifo_wr_dat <= wr_dat;
fifo_wr_en <= wr_req; -- check on NOT full is not necessary according to fifo_generator_ug175.pdf
END GENERATE;
wr_ful <= fifo_full;
rd_emp <= fifo_empty;
usedw <= fifo_usedw;
fifo_rd_en <= rd_req; -- check on NOT empty is not necessary according to fifo_generator_ds317.pdf, so skip it to easy synthesis timing
nxt_rd_val <= fifo_rd_en AND NOT fifo_empty; -- check on NOT empty is necessary for rd_val
nxt_wr_aful <= '0' WHEN TO_UINT(fifo_usedw)<g_nof_words-c_fifo_af_margin ELSE '1';
p_clk : PROCESS(fifo_rst, clk)
BEGIN
IF fifo_rst='1' THEN
wr_aful <= '0';
rd_val <= '0';
ELSIF rising_edge(clk) THEN
wr_aful <= nxt_wr_aful;
rd_val <= nxt_rd_val;
END IF;
END PROCESS;
-- 0 < some threshold < usedw < g_nof_words can be used as FIFO almost_full
-- 0 < usedw < some threshold < g_nof_words can be used as FIFO almost_empty
u_fifo : ENTITY tech_fifo_lib.tech_fifo_sc
GENERIC MAP (
g_technology => g_technology,
g_use_eab => c_use_eab,
g_dat_w => g_dat_w,
g_nof_words => g_nof_words
)
PORT MAP (
aclr => fifo_rst,
clock => clk,
data => fifo_wr_dat,
rdreq => fifo_rd_en,
wrreq => fifo_wr_en,
empty => fifo_empty,
full => fifo_full,
q => rd_dat,
usedw => fifo_usedw
);
proc_common_fifo_asserts("common_fifo_sc", g_note_is_ful, g_fail_rd_emp, fifo_rst, clk, fifo_full, fifo_wr_en, clk, fifo_empty, fifo_rd_en);
END str;
...@@ -36,8 +36,8 @@ ...@@ -36,8 +36,8 @@
LIBRARY ieee; LIBRARY ieee;
USE ieee.std_logic_1164.all; USE ieee.std_logic_1164.all;
LIBRARY common_lib; LIBRARY technology_lib;
USE common_lib.common_pkg.ALL; USE technology_lib.technology_pkg.ALL;
LIBRARY altera_mf; LIBRARY altera_mf;
USE altera_mf.all; USE altera_mf.all;
...@@ -57,9 +57,9 @@ ENTITY altera_mf_fifo_dc IS ...@@ -57,9 +57,9 @@ ENTITY altera_mf_fifo_dc IS
wrreq : IN STD_LOGIC ; wrreq : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0); q : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
rdempty : OUT STD_LOGIC ; rdempty : OUT STD_LOGIC ;
rdusedw : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0); rdusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0);
wrfull : OUT STD_LOGIC ; wrfull : OUT STD_LOGIC ;
wrusedw : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0) wrusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
); );
END altera_mf_fifo_dc; END altera_mf_fifo_dc;
...@@ -67,10 +67,10 @@ END altera_mf_fifo_dc; ...@@ -67,10 +67,10 @@ END altera_mf_fifo_dc;
ARCHITECTURE SYN OF altera_mf_fifo_dc IS ARCHITECTURE SYN OF altera_mf_fifo_dc IS
SIGNAL sub_wire0 : STD_LOGIC ; SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0); SIGNAL sub_wire1 : STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC ; SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0); SIGNAL sub_wire3 : STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0); SIGNAL sub_wire4 : STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0);
...@@ -93,23 +93,23 @@ ARCHITECTURE SYN OF altera_mf_fifo_dc IS ...@@ -93,23 +93,23 @@ ARCHITECTURE SYN OF altera_mf_fifo_dc IS
wrclk : IN STD_LOGIC ; wrclk : IN STD_LOGIC ;
rdempty : OUT STD_LOGIC ; rdempty : OUT STD_LOGIC ;
rdreq : IN STD_LOGIC ; rdreq : IN STD_LOGIC ;
wrusedw : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0); wrusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0);
aclr : IN STD_LOGIC ; aclr : IN STD_LOGIC ;
wrfull : OUT STD_LOGIC ; wrfull : OUT STD_LOGIC ;
rdclk : IN STD_LOGIC ; rdclk : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0); q : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
wrreq : IN STD_LOGIC ; wrreq : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0); data : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
rdusedw : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0) rdusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
); );
END COMPONENT; END COMPONENT;
BEGIN BEGIN
rdempty <= sub_wire0; rdempty <= sub_wire0;
wrusedw <= sub_wire1(ceil_log2(g_nof_words)-1 DOWNTO 0); wrusedw <= sub_wire1(tech_ceil_log2(g_nof_words)-1 DOWNTO 0);
wrfull <= sub_wire2; wrfull <= sub_wire2;
q <= sub_wire3(g_dat_w-1 DOWNTO 0); q <= sub_wire3(g_dat_w-1 DOWNTO 0);
rdusedw <= sub_wire4(ceil_log2(g_nof_words)-1 DOWNTO 0); rdusedw <= sub_wire4(tech_ceil_log2(g_nof_words)-1 DOWNTO 0);
dcfifo_component : dcfifo dcfifo_component : dcfifo
GENERIC MAP ( GENERIC MAP (
...@@ -118,7 +118,7 @@ BEGIN ...@@ -118,7 +118,7 @@ BEGIN
lpm_showahead => "OFF", lpm_showahead => "OFF",
lpm_type => "dcfifo", lpm_type => "dcfifo",
lpm_width => g_dat_w, lpm_width => g_dat_w,
lpm_widthu => ceil_log2(g_nof_words), lpm_widthu => tech_ceil_log2(g_nof_words),
overflow_checking => "ON", overflow_checking => "ON",
rdsync_delaypipe => 5, rdsync_delaypipe => 5,
underflow_checking => "ON", underflow_checking => "ON",
......
...@@ -36,8 +36,8 @@ ...@@ -36,8 +36,8 @@
LIBRARY ieee; LIBRARY ieee;
USE ieee.std_logic_1164.all; USE ieee.std_logic_1164.all;
LIBRARY common_lib; LIBRARY technology_lib;
USE common_lib.common_pkg.ALL; USE technology_lib.technology_pkg.ALL;
LIBRARY altera_mf; LIBRARY altera_mf;
USE altera_mf.all; USE altera_mf.all;
...@@ -58,9 +58,9 @@ ENTITY altera_mf_fifo_dc_mixed_widths IS ...@@ -58,9 +58,9 @@ ENTITY altera_mf_fifo_dc_mixed_widths IS
wrreq : IN STD_LOGIC ; wrreq : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (g_rddat_w-1 DOWNTO 0); q : OUT STD_LOGIC_VECTOR (g_rddat_w-1 DOWNTO 0);
rdempty : OUT STD_LOGIC ; rdempty : OUT STD_LOGIC ;
rdusedw : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words*g_wrdat_w/g_rddat_w)-1 DOWNTO 0); rdusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words*g_wrdat_w/g_rddat_w)-1 DOWNTO 0);
wrfull : OUT STD_LOGIC ; wrfull : OUT STD_LOGIC ;
wrusedw : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0) wrusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
); );
END altera_mf_fifo_dc_mixed_widths; END altera_mf_fifo_dc_mixed_widths;
...@@ -121,8 +121,8 @@ BEGIN ...@@ -121,8 +121,8 @@ BEGIN
lpm_showahead => "OFF", lpm_showahead => "OFF",
lpm_type => "dcfifo", lpm_type => "dcfifo",
lpm_width => g_wrdat_w, lpm_width => g_wrdat_w,
lpm_widthu => ceil_log2(g_nof_words), lpm_widthu => tech_ceil_log2(g_nof_words),
lpm_widthu_r => ceil_log2(g_nof_words*g_wrdat_w/g_rddat_w), lpm_widthu_r => tech_ceil_log2(g_nof_words*g_wrdat_w/g_rddat_w),
lpm_width_r => g_rddat_w, lpm_width_r => g_rddat_w,
overflow_checking => "ON", overflow_checking => "ON",
rdsync_delaypipe => 5, rdsync_delaypipe => 5,
......
...@@ -36,8 +36,8 @@ ...@@ -36,8 +36,8 @@
LIBRARY ieee; LIBRARY ieee;
USE ieee.std_logic_1164.all; USE ieee.std_logic_1164.all;
LIBRARY common_lib; LIBRARY technology_lib;
USE common_lib.common_pkg.ALL; USE technology_lib.technology_pkg.ALL;
LIBRARY altera_mf; LIBRARY altera_mf;
USE altera_mf.all; USE altera_mf.all;
...@@ -58,7 +58,7 @@ ENTITY altera_mf_fifo_sc IS ...@@ -58,7 +58,7 @@ ENTITY altera_mf_fifo_sc IS
empty : OUT STD_LOGIC ; empty : OUT STD_LOGIC ;
full : OUT STD_LOGIC ; full : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0) ; q : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0) ;
usedw : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0) usedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
); );
END altera_mf_fifo_sc; END altera_mf_fifo_sc;
...@@ -87,7 +87,7 @@ ARCHITECTURE SYN OF altera_mf_fifo_sc IS ...@@ -87,7 +87,7 @@ ARCHITECTURE SYN OF altera_mf_fifo_sc IS
); );
PORT ( PORT (
clock : IN STD_LOGIC ; clock : IN STD_LOGIC ;
usedw : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0); usedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0);
empty : OUT STD_LOGIC ; empty : OUT STD_LOGIC ;
full : OUT STD_LOGIC ; full : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0); q : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
...@@ -112,7 +112,7 @@ BEGIN ...@@ -112,7 +112,7 @@ BEGIN
lpm_showahead => "OFF", lpm_showahead => "OFF",
lpm_type => "scfifo", lpm_type => "scfifo",
lpm_width => g_dat_w, lpm_width => g_dat_w,
lpm_widthu => ceil_log2(g_nof_words), lpm_widthu => tech_ceil_log2(g_nof_words),
overflow_checking => "ON", overflow_checking => "ON",
underflow_checking => "ON", underflow_checking => "ON",
use_eab => g_use_eab use_eab => g_use_eab
......
...@@ -6,10 +6,13 @@ build_sim_dir = $HDL_BUILD_DIR ...@@ -6,10 +6,13 @@ build_sim_dir = $HDL_BUILD_DIR
build_synth_dir = build_synth_dir =
synth_files = synth_files =
altera_mf_ram_cr_cw.vhd
altera_mf_ram_crw_crw.vhd
altera_mf_ram_crwk_crw.vhd altera_mf_ram_crwk_crw.vhd
altera_mf_ram_crw_crw.vhd
altera_mf_ram_cr_cw.vhd
altera_mf_ram_r_w.vhd altera_mf_ram_r_w.vhd
altera_mf_rom_r.vhd altera_mf_rom_r.vhd
altera_mf_fifo_dc_mixed_widths.vhd
altera_mf_fifo_dc.vhd
altera_mf_fifo_sc.vhd
test_bench_files = test_bench_files =
hdl_lib_name = technology_fifo hdl_lib_name = tech_fifo
hdl_library_clause_name = technology_fifo_lib hdl_library_clause_name = tech_fifo_lib
hdl_lib_uses = technology ip_altera_mf hdl_lib_uses = technology ip_altera_mf
build_sim_dir = $HDL_BUILD_DIR build_sim_dir = $HDL_BUILD_DIR
......
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