- Switched fail and ok in reg map
- Removed comments  

Removed internal DDR memory model (now needs to be instantiated in tb). Use dedicated records for DDR3 and DDR4 phy interfaces, instead of the combined record.

Removed g_use_ddr_memory_model so the DDR memory model code is not seen/needed by synthesis. Instead only support DDR memory model instantiation in test bench.

Renamed ctlr_mosi into ctlr_tech_mosi for the technology IP side to more clearly distinghuis it from ctrl_drv_mosi for the IO driver side.

splitted the terminationcontrol lines from the record types 't_tech_ddr_phy_in' and 't_tech_ddr_phy_ou'

Renamed key hdl_lib_uses into hdl_lib_uses_synth and added new key hdl_lib_uses_sim for extra test_bench_files library dependencies.

Use g_rd_fifo_af_margin to fit one (DDR3 IP) or more (DDR4 IP) rd burst accesses of g_tech_ddr.maxburstsize each.

Improved check on snk_diag_res by placing it after the read FIFO has been read empty. No need for using v_diag_first_rd to ensure that snk_diag_res_val has become 1.

Improved stimuli using generics and functions to define the write and read block accesses. Distinghuis between tests for DDR3 and DDR4, because DDR4 model simulates about 20x slower.

Added g_sim, when TRUE then use internal DDR memory model in tech_ddr component. When FALSE use DDR memory model in test bench.

Only need to reset the state reg, do not reset the other signals to easy timing closure. Use natural for burst_wr_cnt instead of slv.