Eric Kooistra
authored
Added g_sim, when TRUE then use internal DDR memory model in tech_ddr component. When FALSE use DDR memory model in test bench.
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| Name | Last commit | Last update |
|---|---|---|
| .. | ||
| src/vhdl | ||
| tb/vhdl | ||
| ddr.vhd | ||
| ddr_pkg.vhd | ||
| ddr_testdriver.vhd | ||
| hdllib.cfg | ||