- Jan 05, 2015
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Eric Kooistra authored
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Eric Kooistra authored
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Eric Kooistra authored
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Eric Kooistra authored
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- Dec 23, 2014
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Eric Kooistra authored
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Eric Kooistra authored
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Eric Kooistra authored
Use same string lenght for all g_mode options, to avoid warning on always false in if statement when lengths do not match.
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Eric Kooistra authored
Redefined write flush modes. Now the flush is still under control by dvr_flush_en, and disabled when kept tied to '0'.
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Eric Kooistra authored
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Eric Kooistra authored
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Eric Kooistra authored
Clarified clock domains and use ctlr_clk_out and ctlr_clk_in to make ctlr_clk available in same delta-cycle.
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Eric Kooistra authored
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- Dec 22, 2014
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Eric Kooistra authored
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Eric Kooistra authored
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Eric Kooistra authored
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Eric Kooistra authored
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Eric Kooistra authored
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Eric Kooistra authored
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Eric Kooistra authored
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Eric Kooistra authored
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Eric Kooistra authored
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- Dec 19, 2014
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Eric Kooistra authored
Instantiate tech_ddr_lib.tech_ddr_memory_model. Use dp_clk for rd and wr. DDR3 access starts but diagnostic result fails.diff
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Eric Kooistra authored
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Eric Kooistra authored
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Eric Kooistra authored
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Eric Kooistra authored
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- Dec 18, 2014
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Eric Kooistra authored
Ported $UNB ddr3_flush_ctrl.vhd to $RADIOHDL io_ddr_driver_flush_ctrl.vhd. Initial version, still needs to be compiled and simulated with tb_io_ddr.vhd.
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Eric Kooistra authored
Ported $UNB ddr3.vhd to $RADIOHDL io_ddr.vhd. Initial version, still needs to be compiled and simulated with tb_io_ddr.vhd.
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- Nov 28, 2014
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Jonathan Hargreaves authored
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