use func_tech_ddr_dq_address() for end_address, start_address and for cur_addr.

libraries/io/ddr/src/vhdl/io_ddr_driver.vhd

@@ -35,8 +35,8 @@ ENTITY io_ddr_driver IS
     clk                : IN  STD_LOGIC;
     rst                : IN  STD_LOGIC;
 
-    ctlr_rdy           : IN  STD_LOGIC;
     ctlr_init_done     : IN  STD_LOGIC;
+    ctlr_rdy           : IN  STD_LOGIC;
     ctlr_burst         : OUT STD_LOGIC;
     ctlr_burst_size    : OUT STD_LOGIC_VECTOR(g_tech_ddr.maxburstsize_w-1 DOWNTO 0);
     ctlr_wr_req        : OUT STD_LOGIC;   
@@ -61,8 +61,7 @@ END io_ddr_driver;
 
 ARCHITECTURE str OF io_ddr_driver IS
 
-  CONSTANT c_chip_addr_w        : NATURAL := ceil_log2(g_tech_ddr.cs_w); --Chip sel lines converted to logical address
-  CONSTANT c_address_w          : NATURAL := c_chip_addr_w + g_tech_ddr.ba_w + g_tech_ddr.a_w + g_tech_ddr.a_col_w +1; -- 1 bit added to detect overflow
+  CONSTANT c_address_w          : NATURAL := func_tech_ddr_dq_address_w(g_tech_ddr) + 1;  -- 1 bit added to detect overflow
  
   CONSTANT c_margin             : NATURAL := 2; -- wr_burst_size is updated one cycle after reading actual nof available words.
                                                 -- Subtract two (wr_fifo_usedw and wr_burst_size are both registered) so we cannot 
@@ -264,13 +263,10 @@ BEGIN
     END CASE;
   END PROCESS;
 
-  end_address   <= RESIZE_UVEC(  end_addr.chip &  end_addr.bank  &   end_addr.row(g_tech_ddr.a_w-1 DOWNTO 0) &   end_addr.column(g_tech_ddr.a_col_w-1 DOWNTO 0), c_address_w);  
-  start_address <= RESIZE_UVEC(start_addr.chip & start_addr.bank & start_addr.row(g_tech_ddr.a_w-1 DOWNTO 0) & start_addr.column(g_tech_ddr.a_col_w-1 DOWNTO 0), c_address_w); 
+  end_address   <= func_tech_ddr_dq_address(  end_addr, g_tech_ddr, c_address_w);
+  start_address <= func_tech_ddr_dq_address(start_addr, g_tech_ddr, c_address_w);
   
-  cur_addr.chip(  c_chip_addr_w     -1 DOWNTO 0) <= cur_address(c_chip_addr_w+g_tech_ddr.ba_w+g_tech_ddr.a_w+g_tech_ddr.a_col_w-1 DOWNTO g_tech_ddr.ba_w+g_tech_ddr.a_w+g_tech_ddr.a_col_w); 
-  cur_addr.bank(  g_tech_ddr.ba_w   -1 DOWNTO 0) <= cur_address(              g_tech_ddr.ba_w+g_tech_ddr.a_w+g_tech_ddr.a_col_w-1 DOWNTO                 g_tech_ddr.a_w+g_tech_ddr.a_col_w);
-  cur_addr.row(   g_tech_ddr.a_w    -1 DOWNTO 0) <= cur_address(                              g_tech_ddr.a_w+g_tech_ddr.a_col_w-1 DOWNTO                                g_tech_ddr.a_col_w);
-  cur_addr.column(g_tech_ddr.a_col_w-1 DOWNTO 0) <= cur_address(                                             g_tech_ddr.a_col_w-1 DOWNTO                                                 0);
+  cur_addr <= func_tech_ddr_dq_address(cur_address, g_tech_ddr);
   
 END str;