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Commit c41d1a7e authored by Eric Kooistra's avatar Eric Kooistra
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Instantiate tech_ddr_lib.tech_ddr_memory_model. Use dp_clk for rd and wr. DDR3... 

Instantiate tech_ddr_lib.tech_ddr_memory_model. Use dp_clk for rd and wr. DDR3 access starts but diagnostic result fails.diff
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libraries/io/ddr/tb/vhdl/tb_io_ddr.vhd
+ 33
− 79
View file @ c41d1a7e
......@@ -39,7 +39,7 @@ USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE common_lib.tb_common_mem_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
USE technology_lib.technology_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL;
USE tech_ddr_lib.tech_ddr_pkg.ALL;
ENTITY tb_io_ddr IS
......@@ -48,16 +48,17 @@ END ENTITY tb_io_ddr;
ARCHITECTURE str of tb_io_ddr IS
CONSTANT c_ctlr_ref_clk_period : TIME := 5 ns; -- 200 MHz
CONSTANT c_dp_clk_period : TIME := 5 ns; -- 200 MHz
CONSTANT c_tech_ddr : t_c_tech_ddr := c_tech_ddr_4g_800m;
CONSTANT c_tech_ddr : t_c_tech_ddr := c_tech_ddr3_4g_800m_master;
CONSTANT c_data_w : NATURAL := 256; --32;
CONSTANT c_data_w : NATURAL := 256; --32;
SIGNAL ctlr_ref_clk : STD_LOGIC := '0';
SIGNAL ctlr_ref_rst : STD_LOGIC := '1';
SIGNAL tb_end : STD_LOGIC := '0';
SIGNAL ctlr_gen_clk : STD_LOGIC;
SIGNAL ctlr_gen_rst : STD_LOGIC;
SIGNAL ctlr_ref_clk : STD_LOGIC := '0';
SIGNAL ctlr_ref_rst : STD_LOGIC;
SIGNAL tb_end : STD_LOGIC := '0';
SIGNAL dp_clk : STD_LOGIC := '0';
SIGNAL dp_rst : STD_LOGIC;
SIGNAL ctlr_rdy : STD_LOGIC;
SIGNAL ctlr_init_done : STD_LOGIC;
......@@ -90,14 +91,13 @@ ARCHITECTURE str of tb_io_ddr IS
SIGNAL phy_io : t_tech_ddr_phy_io;
SIGNAL phy_ou : t_tech_ddr_phy_ou;
SIGNAL ras_n : STD_LOGIC_VECTOR(0 DOWNTO 0);
SIGNAL cas_n : STD_LOGIC_VECTOR(0 DOWNTO 0);
SIGNAL we_n : STD_LOGIC_VECTOR(0 DOWNTO 0);
BEGIN
ctlr_ref_clk <= NOT(ctlr_ref_clk) OR tb_end AFTER c_ctlr_ref_clk_period/2;
ctlr_ref_rst <= '0' AFTER 100 ns;
ctlr_ref_clk <= NOT ctlr_ref_clk OR tb_end AFTER c_ctlr_ref_clk_period/2;
ctlr_ref_rst <= '1', '0' AFTER 100 ns;
dp_clk <= NOT dp_clk OR tb_end AFTER c_dp_clk_period/2;
dp_rst <= '1', '0' AFTER 100 ns;
dvr_start_addr <= c_tech_ddr_addr_lo;
dvr_end_addr <= c_tech_ddr_addr_hi_sim;
......@@ -112,7 +112,7 @@ BEGIN
WAIT UNTIL ctlr_init_done = '1';
FOR i IN 0 TO 1 LOOP
WAIT UNTIL rising_edge(ctlr_gen_clk); -- Give the driver FSM a cycle to go into idle mode
WAIT UNTIL rising_edge(dp_clk); -- Give the driver FSM a cycle to go into idle mode
END LOOP;
-- START WRITE
......@@ -120,7 +120,7 @@ BEGIN
dvr_wr_not_rd <= '1';
dvr_en <= '1';
WAIT UNTIL rising_edge(ctlr_gen_clk);
WAIT UNTIL rising_edge(dp_clk);
dvr_en <= '0';
......@@ -134,7 +134,7 @@ BEGIN
dvr_wr_not_rd <= '0';
dvr_en <= '1';
WAIT UNTIL rising_edge(ctlr_gen_clk);
WAIT UNTIL rising_edge(dp_clk);
dvr_en <= '0';
......@@ -157,8 +157,8 @@ BEGIN
g_nof_streams => 1
)
PORT MAP (
rst => ctlr_gen_rst,
clk => ctlr_gen_clk,
rst => dp_rst,
clk => dp_clk,
snk_out_arr(0) => rd_siso,
snk_in_arr(0) => rd_sosi,
......@@ -175,62 +175,10 @@ BEGIN
src_val_cnt(0) => src_val_cnt
);
gen_ddr_4g_memory_model : IF func_tech_ddr_module_size(c_tech_ddr) = 4 GENERATE
u_4gb_ddr3_memory_model : COMPONENT alt_mem_if_ddr3_mem_model_top_ddr3_mem_if_dm_pins_en_mem_if_dqsn_en
GENERIC MAP (
MEM_IF_ADDR_WIDTH => 15,
MEM_IF_ROW_ADDR_WIDTH => 15,
MEM_IF_COL_ADDR_WIDTH => 10,
MEM_IF_CS_PER_RANK => 1,
MEM_IF_CONTROL_WIDTH => 1,
MEM_IF_DQS_WIDTH => 8,
MEM_IF_CS_WIDTH => 2,
MEM_IF_BANKADDR_WIDTH => 3,
MEM_IF_DQ_WIDTH => 64,
MEM_IF_CK_WIDTH => 2,
MEM_IF_CLK_EN_WIDTH => 2,
DEVICE_WIDTH => 1,
MEM_TRCD => 6,
MEM_TRTP => 3,
MEM_DQS_TO_CLK_CAPTURE_DELAY => 100,
MEM_CLK_TO_DQS_CAPTURE_DELAY => 100000,
MEM_IF_ODT_WIDTH => 2,
MEM_MIRROR_ADDRESSING_DEC => 0,
MEM_REGDIMM_ENABLED => false,
DEVICE_DEPTH => 1,
MEM_GUARANTEED_WRITE_INIT => false,
MEM_VERBOSE => true,
MEM_INIT_EN => false,
MEM_INIT_FILE => "",
DAT_DATA_WIDTH => 32
)
PORT MAP (
mem_a => phy_ou.a(c_tech_ddr.a_w-1 DOWNTO 0), -- memory.mem_a
mem_ba => phy_ou.ba, -- .mem_ba
mem_ck => phy_io.clk, -- .mem_ck
mem_ck_n => phy_io.clk_n, -- .mem_ck_n
mem_cke => phy_ou.cke(c_tech_ddr.cs_w-1 DOWNTO 0), -- .mem_cke
mem_cs_n => phy_ou.cs_n(c_tech_ddr.cs_w-1 DOWNTO 0), -- .mem_cs_n
mem_dm => phy_ou.dm, -- .mem_dm
mem_ras_n => ras_n, -- .mem_ras_n
mem_cas_n => cas_n, -- .mem_cas_n
mem_we_n => we_n, -- .mem_we_n
mem_reset_n => phy_ou.reset_n, -- .mem_reset_n
mem_dq => phy_io.dq, -- .mem_dq
mem_dqs => phy_io.dqs, -- .mem_dqs
mem_dqs_n => phy_io.dqs_n, -- .mem_dqs_n
mem_odt => phy_ou.odt -- .mem_odt
);
ras_n(0) <= phy_ou.ras_n;
cas_n(0) <= phy_ou.cas_n;
we_n(0) <= phy_ou.we_n;
END GENERATE;
u_io_ddr: ENTITY work.io_ddr
GENERIC MAP(
g_technology => c_tech_select_default,
g_ddr => c_tech_ddr,
g_tech_ddr => c_tech_ddr,
g_wr_data_w => c_data_w,
g_rd_data_w => c_data_w
)
......@@ -238,9 +186,6 @@ BEGIN
ctlr_ref_clk => ctlr_ref_clk,
ctlr_ref_rst => ctlr_ref_rst,
ctlr_gen_clk => ctlr_gen_clk,
ctlr_gen_rst => ctlr_gen_rst,
ctlr_init_done => ctlr_init_done,
ctlr_rdy => ctlr_rdy,
......@@ -250,8 +195,8 @@ BEGIN
dvr_wr_not_rd => dvr_wr_not_rd,
dvr_done => dvr_done,
wr_clk => ctlr_gen_clk,
wr_rst => ctlr_gen_rst,
wr_clk => dp_clk,
wr_rst => dp_rst,
wr_sosi => wr_sosi,
wr_siso => wr_siso,
......@@ -259,14 +204,23 @@ BEGIN
rd_sosi => rd_sosi,
rd_siso => rd_siso,
rd_clk => ctlr_gen_clk,
rd_rst => ctlr_gen_rst,
rd_clk => dp_clk,
rd_rst => dp_rst,
phy_ou => phy_ou,
phy_io => phy_io,
phy_in => phy_in
);
u_tech_ddr_memory_model : ENTITY tech_ddr_lib.tech_ddr_memory_model
GENERIC MAP (
g_tech_ddr => c_tech_ddr
)
PORT MAP (
mem_in => phy_ou,
mem_io => phy_io
);
END ARCHITECTURE str;
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