placed u_sim_model under gen_ddr3 such that it will not be used for DDR4 simulation, the sim_model does not work when simulating the testbench for unb2b

Removed dvr_clk, because it is the mm_clk. Fixed use g_cross_domain_dvr_ctlr = TRUE to get between mm_clk and ctlr_clk_in.

Removed clock domain crossing logic for this control register, because that is done by io_ddr_cross_domain.vhd in io_ddr.vhd. Removed cal_fail and cal_ok, because these are already available via the io_ddr status register.