Add and verify ddr_gigabytes field in reg_io_ddr.

libraries/io/ddr/ddr.peripheral.yaml

@@ -18,8 +18,9 @@ peripherals:
         fields:
           - - field_name: reg_io_ddr 
               field_description: |
-                "IO DDR status bits concatenated: 
-                 ctlr_tech_mosi.wr & ctlr_tech_miso.rdval & ctlr_tech_miso.cal_fail      & ctlr_tech_miso.cal_ok 
+                "IO DDR status bits concatenated:
+                 ddr_gigabytes[7:0] &
+                 ctlr_tech_mosi.wr & ctlr_tech_miso.rdval & ctlr_tech_miso.cal_fail      & ctlr_tech_miso.cal_ok &
                  ctlr_rst_out_i    & ctlr_wr_flush_en     & ctlr_tech_miso.waitrequest_n & ctlr_tech_miso.done"
               address_offset: 0 * MM_BUS_SIZE
               access_mode: RO

libraries/io/ddr/src/vhdl/io_ddr.vhd

@@ -234,6 +234,7 @@ ARCHITECTURE str OF io_ddr IS
   CONSTANT c_wr_use_ctrl       : BOOLEAN := sel_a_b(g_wr_flush_mode="SOP", TRUE, FALSE);
   CONSTANT c_wr_fifo_use_ctrl  : BOOLEAN := c_wr_use_sync OR c_wr_use_ctrl;
   
+  CONSTANT c_ddr_gigabytes    : NATURAL := func_tech_ddr_module_size(g_tech_ddr);  -- units GiByte
   CONSTANT c_ctlr_address_w    : NATURAL := func_tech_ddr_ctlr_address_w(g_tech_ddr);
   CONSTANT c_ctlr_data_w       : NATURAL := func_tech_ddr_ctlr_data_w(g_tech_ddr);
   CONSTANT c_wr_fifo_depth     : NATURAL := g_wr_fifo_depth * (c_ctlr_data_w/g_wr_data_w);  -- get FIFO depth at write side
@@ -520,7 +521,8 @@ BEGIN
   mm_reg_io_ddr <= RESIZE_UVEC(rd_fifo_full_reg & wr_fifo_full_reg, c_mem_reg_dat_w) & 
                    RESIZE_UVEC(ctlr_wr_fifo_usedw, c_mem_reg_dat_w) & 
                    RESIZE_UVEC(ctlr_rd_fifo_usedw, c_mem_reg_dat_w) & 
-                   RESIZE_UVEC(ctlr_tech_mosi.wr & ctlr_tech_miso.rdval & ctlr_tech_miso.cal_fail      & ctlr_tech_miso.cal_ok & 
+                   RESIZE_UVEC(TO_UVEC(c_ddr_gigabytes, 8) &
+                               ctlr_tech_mosi.wr & ctlr_tech_miso.rdval & ctlr_tech_miso.cal_fail      & ctlr_tech_miso.cal_ok &
                                ctlr_rst_out_i    & ctlr_wr_flush_en     & ctlr_tech_miso.waitrequest_n & ctlr_tech_miso.done, c_mem_reg_dat_w);   
   
   u_reg_map : ENTITY common_lib.common_reg_r_w_dc

libraries/io/ddr/tb/vhdl/tb_io_ddr.vhd

@@ -72,7 +72,7 @@ ARCHITECTURE str of tb_io_ddr IS
   CONSTANT c_sim_ddr                  : t_c_tech_ddr := func_tech_sel_ddr(g_technology, c_tech_ddr3_sim_16k, c_tech_ddr4_sim_16k);
   CONSTANT c_tech_ddr                 : t_c_tech_ddr := func_tech_sel_ddr(g_sim_model, c_sim_ddr, c_mem_ddr);
   
-  CONSTANT c_gigabytes                : NATURAL := func_tech_ddr_module_size(c_tech_ddr);
+  CONSTANT c_exp_gigabytes            : NATURAL := func_tech_ddr_module_size(c_tech_ddr);
 
   CONSTANT c_dp_clk_period            : TIME := 5 ns;   -- 200 MHz
   CONSTANT c_mm_clk_period            : TIME := 8 ns;   -- 125 MHz
@@ -165,7 +165,8 @@ ARCHITECTURE str of tb_io_ddr IS
   SIGNAL dbg_c_ctlr_wr_not_rd_arr     : STD_LOGIC_VECTOR(0 TO c_nof_access-1)  := c_ctlr_wr_not_rd_arr;
   
   SIGNAL dbg_c_tech_ddr               : t_c_tech_ddr := c_tech_ddr;
-  SIGNAL dbg_c_gigabytes              : NATURAL := c_gigabytes;  -- = 0 for sim model, else nof GB
+  SIGNAL dbg_c_exp_gigabytes          : NATURAL := c_exp_gigabytes;  -- = 0 for sim model, else nof GB
+  SIGNAL ddr_gigabytes                : NATURAL;
   SIGNAL dbg_c_dp_data_w              : NATURAL := c_dp_data_w;
   SIGNAL dbg_c_wr_fifo_depth          : NATURAL := c_wr_fifo_depth;
   SIGNAL dbg_c_rd_fifo_depth          : NATURAL := c_rd_fifo_depth;
@@ -182,12 +183,14 @@ ARCHITECTURE str of tb_io_ddr IS
   SIGNAL mm_clk               : STD_LOGIC := '0';
   SIGNAL mm_rst               : STD_LOGIC;
 
+  -- Status interface
+  SIGNAL reg_io_ddr_mosi      : t_mem_mosi := c_mem_mosi_rst;
+  SIGNAL reg_io_ddr_miso      : t_mem_miso := c_mem_miso_rst;
+
+  -- Driver interface
   SIGNAL dvr_miso             : t_mem_ctlr_miso;
   SIGNAL dvr_mosi             : t_mem_ctlr_mosi;   
   
-  SIGNAL reg_io_ddr_mosi      : t_mem_mosi := c_mem_mosi_rst;           
-  SIGNAL reg_io_ddr_miso      : t_mem_miso := c_mem_miso_rst;           
-  
   SIGNAL dvr_done             : STD_LOGIC;
   SIGNAL dvr_en               : STD_LOGIC;
   SIGNAL dvr_wr_not_rd        : STD_LOGIC;
@@ -260,8 +263,17 @@ BEGIN
     WAIT FOR 100 ns;
     ctlr_ref_rst      <= '0';
 
+    -- Wait until calibration done (and ctlr_rst released)
     proc_common_wait_until_high(dvr_clk, dvr_done);
     
+    -- Read DDR4 memory size
+    proc_common_wait_cross_clock_domain_latency(mm_clk, dp_clk);
+    proc_mem_mm_bus_rd(0, mm_clk, reg_io_ddr_miso, reg_io_ddr_mosi);
+    proc_mem_mm_bus_rd_latency(1, mm_clk);
+    ddr_gigabytes <= TO_UINT(reg_io_ddr_miso.rddata(15 DOWNTO 8));
+    proc_common_wait_some_cycles(mm_clk, 1);
+    ASSERT ddr_gigabytes = c_exp_gigabytes REPORT "Wrong read memory size" SEVERITY ERROR;
+
     -- Start diagnostics source for write and sink for verify read
     proc_common_wait_some_cycles(dp_clk, 1);
     src_diag_en <= '1';