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Commit d2c123fa authored by Reinier van der Walle's avatar Reinier van der Walle
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placed u_sim_model under gen_ddr3 such that it will not be used for DDR4... 

placed u_sim_model under gen_ddr3 such that it will not be used for DDR4 simulation, the sim_model does not work when simulating the testbench for unb2b
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libraries/io/ddr/tb/vhdl/tb_tb_io_ddr.vhd
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......@@ -65,31 +65,34 @@ BEGIN
-- g_nof_repeat : NATURAL := 1; -- number of stimuli repeats with write flush after each repeat
-- g_wr_flush_mode : STRING := "SYN" -- "VAL", "SOP", "SYN"
u_sim_model : ENTITY work.tb_io_ddr GENERIC MAP ( TRUE, c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, 5 ns, 4, 2500, 2, 1, 1, 1, "VAL") PORT MAP (tb_end_vec(0));
-- FIXME: Sim model does not work for UNB2B, it causes the testbench to timeout. Temporarly placed under gen_ddr3.
-- u_sim_model : ENTITY work.tb_io_ddr GENERIC MAP ( TRUE, c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, 5 ns, 4, 2500, 2, 1, 1, 1, "VAL") PORT MAP (tb_end_vec(0));
gen_ddr3 : IF c_tech_ddr.name="DDR3" GENERATE
u_default : ENTITY work.tb_io_ddr GENERIC MAP (FALSE, c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, 5 ns, 4, 2500, 2, 1, 1, 1, "VAL") PORT MAP (tb_end_vec(0));
u_sim_model : ENTITY work.tb_io_ddr GENERIC MAP ( TRUE, c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, 5 ns, 4, 2500, 2, 1, 1, 1, "VAL") PORT MAP (tb_end_vec(0));
u_default : ENTITY work.tb_io_ddr GENERIC MAP (FALSE, c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, 5 ns, 4, 2500, 2, 1, 1, 1, "VAL") PORT MAP (tb_end_vec(1));
u_fill_wrfifo_on_next_valid : ENTITY work.tb_io_ddr GENERIC MAP (FALSE, c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, 5 ns, 1, 1000, 2, 1, 4, 2, "VAL") PORT MAP (tb_end_vec(1));
u_fill_wrfifo_on_next_sop : ENTITY work.tb_io_ddr GENERIC MAP (FALSE, c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, 5 ns, 1, 1000, 2, 3, 4, 2, "SOP") PORT MAP (tb_end_vec(2));
u_fill_wrfifo_on_next_sync : ENTITY work.tb_io_ddr GENERIC MAP (FALSE, c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, 5 ns, 1, 1000, 2, 4, 1, 2, "SYN") PORT MAP (tb_end_vec(3));
u_fill_wrfifo_on_next_valid : ENTITY work.tb_io_ddr GENERIC MAP (FALSE, c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, 5 ns, 1, 1000, 2, 1, 4, 2, "VAL") PORT MAP (tb_end_vec(2));
u_fill_wrfifo_on_next_sop : ENTITY work.tb_io_ddr GENERIC MAP (FALSE, c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, 5 ns, 1, 1000, 2, 3, 4, 2, "SOP") PORT MAP (tb_end_vec(3));
u_fill_wrfifo_on_next_sync : ENTITY work.tb_io_ddr GENERIC MAP (FALSE, c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, 5 ns, 1, 1000, 2, 4, 1, 2, "SYN") PORT MAP (tb_end_vec(4));
u_cross_domain : ENTITY work.tb_io_ddr GENERIC MAP (FALSE, c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, TRUE, 5 ns, 1, 2500, 1, 2, 3, 1, "VAL") PORT MAP (tb_end_vec(4));
u_mixed_width : ENTITY work.tb_io_ddr GENERIC MAP (FALSE, c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, 5 ns, 8, 2500, 1, 3, 2, 1, "VAL") PORT MAP (tb_end_vec(5));
u_cross_domain : ENTITY work.tb_io_ddr GENERIC MAP (FALSE, c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, TRUE, 5 ns, 1, 2500, 1, 2, 3, 1, "VAL") PORT MAP (tb_end_vec(5));
u_mixed_width : ENTITY work.tb_io_ddr GENERIC MAP (FALSE, c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, 5 ns, 8, 2500, 1, 3, 2, 1, "VAL") PORT MAP (tb_end_vec(6));
u_wr_burst_size_0 : ENTITY work.tb_io_ddr GENERIC MAP (FALSE, c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, 5 ns, 4, 2,10, 3, 3, 2, "VAL") PORT MAP (tb_end_vec(6));
u_wr_burst_size_1 : ENTITY work.tb_io_ddr GENERIC MAP (FALSE, c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, 5 ns, 4, 1,10, 1, 1, 2, "VAL") PORT MAP (tb_end_vec(7));
u_wr_burst_size_0 : ENTITY work.tb_io_ddr GENERIC MAP (FALSE, c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, 5 ns, 4, 2,10, 3, 3, 2, "VAL") PORT MAP (tb_end_vec(7));
u_wr_burst_size_1 : ENTITY work.tb_io_ddr GENERIC MAP (FALSE, c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, 5 ns, 4, 1,10, 1, 1, 2, "VAL") PORT MAP (tb_end_vec(8));
u_cross_dvr_to_faster_ctlr : ENTITY work.tb_io_ddr GENERIC MAP (FALSE, c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, 20 ns, 1, 2500, 1, 1, 4, 1, "VAL") PORT MAP (tb_end_vec(8));
u_cross_dvr_to_slower_ctlr : ENTITY work.tb_io_ddr GENERIC MAP (FALSE, c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, 1 ns, 1, 2500, 1, 1, 4, 1, "VAL") PORT MAP (tb_end_vec(9));
u_cross_dvr_to_faster_ctlr : ENTITY work.tb_io_ddr GENERIC MAP (FALSE, c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, 20 ns, 1, 2500, 1, 1, 4, 1, "VAL") PORT MAP (tb_end_vec(9));
u_cross_dvr_to_slower_ctlr : ENTITY work.tb_io_ddr GENERIC MAP (FALSE, c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, 1 ns, 1, 2500, 1, 1, 4, 1, "VAL") PORT MAP (tb_end_vec(10));
u_sequencer_1_16 : ENTITY work.tb_io_ddr GENERIC MAP (FALSE, c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, 5 ns, 4, 64,10, 1,16, 1, "VAL") PORT MAP (tb_end_vec(10));
u_sequencer_16_1 : ENTITY work.tb_io_ddr GENERIC MAP (FALSE, c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, 5 ns, 4, 64,10,16, 1, 1, "VAL") PORT MAP (tb_end_vec(11));
u_sequencer_1_16 : ENTITY work.tb_io_ddr GENERIC MAP (FALSE, c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, 5 ns, 4, 64,10, 1,16, 1, "VAL") PORT MAP (tb_end_vec(11));
u_sequencer_16_1 : ENTITY work.tb_io_ddr GENERIC MAP (FALSE, c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, 5 ns, 4, 64,10,16, 1, 1, "VAL") PORT MAP (tb_end_vec(12));
END GENERATE;
-- Distinghuis between tests for DDR3 and DDR4, because the Quartus 14.1 ip_arria10 DDR4 model simulates about 40x slower than the Quartus 11.1 ip_stratixiv DDR3 uniphy model.
gen_ddr4 : IF c_tech_ddr.name="DDR4" GENERATE
u_default : ENTITY work.tb_io_ddr GENERIC MAP (FALSE, c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, 5 ns, 4, 2500, 2, 1, 1, 1, "VAL") PORT MAP (tb_end_vec(0));
u_default : ENTITY work.tb_io_ddr GENERIC MAP (FALSE, c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, 5 ns, 4, 2500, 2, 1, 1, 1, "VAL") PORT MAP (tb_end_vec(1));
END GENERATE;
tb_end <= '1' WHEN tb_end_vec=c_tb_end_vec ELSE '0';
......
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