added yaml entries for unb2c_test design

boards/uniboard2c/designs/unb2c_test/unb2c_test.fpga.yaml

+schema_name   : args
+schema_version: 1.0
+schema_type   : fpga
+
+hdl_library_name: unb2c_test
+fpga_name       : unb2c_test
+fpga_description: "FPGA design unb2c_test"
+parameters:
+  - { name: c_nof_streams_1GbE_UDP,             value: 2 }  
+  - { name: c_def_1GbE_block_size,              value: 20 }  
+  - { name: c_nof_streams_10GbE_UDP,            value: 72 }  
+  - { name: c_def_10GbE_block_size,             value: 900 }  
+  - { name: c_nof_streams_qsfp,                 value: 24 }  
+  - { name: c_nof_streams_ring,                 value: 24 }  
+  - { name: c_nof_streams_back0,                value: 24 }  
+  - { name: c_ddr_db_buf_nof_data,              value: 1024 }  
+  - { name: c_nof_streams_jesd204b,             value: 12 }  
+  - { name: c_jesd_db_buf_nof_data,             value: 131072 }  
+
+peripherals:
+  # ctrl_unb2c_board
+  - peripheral_name: unb2c_board/system_info
+    lock_base_address: 0x10000
+    mm_port_names:
+      - ROM_SYSTEM_INFO
+      - PIO_SYSTEM_INFO
+
+  - peripheral_name: unb2c_board/wdi
+    mm_port_names:
+      - REG_WDI
+
+  - peripheral_name: unb2c_board/unb2_fpga_sens
+    mm_port_names:
+      - REG_FPGA_TEMP_SENS
+      - REG_FPGA_VOLTAGE_SENS
+
+  - peripheral_name: unb2c_board/ram_scrap
+    mm_port_names:
+      - RAM_SCRAP
+
+  - peripheral_name: eth/eth
+    mm_port_names:
+      - AVS_ETH_0_TSE
+      - AVS_ETH_0_REG
+      - AVS_ETH_0_RAM
+      
+  - peripheral_name: ppsh/ppsh
+    mm_port_names:
+      - PIO_PPS
+      
+  - peripheral_name: epcs/epcs
+    mm_port_names:
+      - REG_EPCS
+
+  - peripheral_name: dp/dpmm
+    mm_port_names:
+      - REG_DPMM_CTRL
+      - REG_DPMM_DATA
+
+  - peripheral_name: dp/mmdp
+    mm_port_names:
+      - REG_MMDP_CTRL
+      - REG_MMDP_DATA
+
+  - peripheral_name: remu/remu
+    mm_port_names:
+      - REG_REMU
+
+  # Heater 
+  - peripheral_name: util/heater
+    mm_port_names:
+      - REG_HEATER
+
+  # 1GbE
+  - peripheral_name: diag/diag_block_gen
+    peripheral_group: eth_1gbe
+    parameter_overrides:
+      - { name: g_nof_streams, value: c_nof_streams_1GbE_UDP }
+      - { name: g_buf_dat_w, value: 32 }
+      - { name: g_buf_addr_w, value: ceil_log2(c_def_1GbE_block_size) }
+    mm_port_names:
+      - REG_DIAG_BG_1GBE
+      - RAM_DIAG_BG_1GBE
+
+  - peripheral_name: diag/diag_tx_seq
+    peripheral_group: eth_1gbe
+    parameter_overrides:
+      - { name: g_nof_streams, value: c_nof_streams_1GbE_UDP }
+    mm_port_names:
+      - REG_DIAG_TX_SEQ_1GBE
+
+  - peripheral_name: dp/dp_bsn_monitor
+    peripheral_group: eth_1gbe
+    parameter_overrides:
+      - { name: g_nof_streams, value: c_nof_streams_1GbE_UDP }
+    mm_port_names:
+      - REG_BSN_MONITOR_1GBE
+
+  - peripheral_name: diag/diag_data_buffer
+    peripheral_group: eth_1gbe
+    parameter_overrides:
+      - { name: g_nof_streams, value: c_nof_streams_1GbE_UDP }
+      - { name: g_data_w, value: 32 }
+      - { name: g_nof_data, value: c_def_1GbE_block_size }
+    mm_port_names:
+      - REG_DIAG_DATA_BUFFER_1GBE
+      - RAM_DIAG_DATA_BUFFER_1GBE
+
+  - peripheral_name: diag/diag_rx_seq
+    peripheral_group: eth_1gbe
+    parameter_overrides:
+      - { name: g_nof_streams, value: c_nof_streams_1GbE_UDP }
+    mm_port_names:
+      - REG_DIAG_TX_SEQ_1GBE
+
+  # 10GbE
+  - peripheral_name: diag/diag_block_gen
+    peripheral_group: eth_10gbe
+    parameter_overrides:
+      - { name: g_nof_streams, value: c_nof_streams_10GbE_UDP }
+      - { name: g_buf_dat_w, value: 64 }
+      - { name: g_buf_addr_w, value: ceil_log2(c_def_10GbE_block_size) }
+    mm_port_names:
+      - REG_DIAG_BG_10GBE
+      - RAM_DIAG_BG_10GBE
+
+  - peripheral_name: diag/diag_tx_seq
+    peripheral_group: eth_10gbe
+    parameter_overrides:
+      - { name: g_nof_streams, value: c_nof_streams_10GbE_UDP }
+    mm_port_names:
+      - REG_DIAG_TX_SEQ_10GBE
+
+  - peripheral_name: dp/dp_bsn_monitor
+    peripheral_group: eth_10gbe
+    parameter_overrides:
+      - { name: g_nof_streams, value: c_nof_streams_10GbE_UDP }
+    mm_port_names:
+      - REG_BSN_MONITOR_10GBE
+
+  - peripheral_name: diag/diag_data_buffer
+    peripheral_group: eth_10gbe
+    parameter_overrides:
+      - { name: g_nof_streams, value: c_nof_streams_10GbE_UDP }
+      - { name: g_data_w, value: 64 }
+      - { name: g_nof_data, value: c_def_10GbE_block_size }
+    mm_port_names:
+      - REG_DIAG_DATA_BUFFER_10GBE
+      - RAM_DIAG_DATA_BUFFER_10GBE
+
+  - peripheral_name: diag/diag_rx_seq
+    peripheral_group: eth_10gbe
+    parameter_overrides:
+      - { name: g_nof_streams, value: c_nof_streams_10GbE_UDP }
+    mm_port_names:
+      - REG_DIAG_TX_SEQ_10GBE
+
+  - peripheral_name: tr_10GbE/tr_10GbE_unb2legacy
+    peripheral_group: qsfp_ring
+    parameter_overrides:
+      - { name: g_nof_macs, value: c_nof_streams_qsfp + c_nof_streams_ring }
+    mm_port_names:
+      - REG_TR_10GBE_QSFP_RING
+
+  - peripheral_name: tr_10GbE/tr_10GbE_eth10g
+    peripheral_group: qsfp_ring
+    parameter_overrides:
+      - { name: g_nof_macs, value: c_nof_streams_qsfp + c_nof_streams_ring }
+    mm_port_names:
+      - REG_ETH10G_QSFP_RING
+
+  - peripheral_name: tr_10GbE/tr_10GbE_unb2legacy
+    peripheral_group: back0
+    parameter_overrides:
+      - { name: g_nof_macs, value: c_nof_streams_back0 }
+    mm_port_names:
+      - REG_TR_10GBE_BACK0
+
+  - peripheral_name: tr_10GbE/tr_10GbE_eth10g
+    peripheral_group: back0
+    parameter_overrides:
+      - { name: g_nof_macs, value: c_nof_streams_back0 }
+    mm_port_names:
+      - REG_ETH10G_BACK0
+
+  # DDR4 : MB I 
+  - peripheral_name: ddr/io_ddr
+    peripheral_group: MB_I
+    mm_port_names:
+      - REG_IO_DDR_MB_I
+
+  - peripheral_name: diag/diag_tx_seq
+    peripheral_group: MB_I
+    mm_port_names:
+      - REG_DIAG_TX_SEQ_DDR_MB_I
+
+  - peripheral_name: diag/diag_rx_seq
+    peripheral_group: MB_I
+    mm_port_names:
+      - REG_DIAG_RX_SEQ_DDR_MB_I
+
+  - peripheral_name: diag/diag_data_buffer
+    peripheral_group: ddr_MB_I
+    parameter_overrides:
+      - { name: g_data_w, value: 32 }
+      - { name: g_nof_data, value: c_ddr_db_buf_nof_data }
+    mm_port_names:
+      - REG_DIAG_DATA_BUFFER_DDR_MB_I
+      - RAM_DIAG_DATA_BUFFER_DDR_MB_I
+
+  # DDR4 : MB II 
+  - peripheral_name: ddr/io_ddr
+    peripheral_group: MB_II
+    mm_port_names:
+      - REG_IO_DDR_MB_II
+
+  - peripheral_name: diag/diag_tx_seq
+    peripheral_group: MB_II
+    mm_port_names:
+      - REG_DIAG_TX_SEQ_DDR_MB_II
+
+  - peripheral_name: diag/diag_rx_seq
+    peripheral_group: MB_II
+    mm_port_names:
+      - REG_DIAG_RX_SEQ_DDR_MB_II
+
+  - peripheral_name: diag/diag_data_buffer
+    peripheral_group: ddr_MB_II
+    parameter_overrides:
+      - { name: g_data_w, value: 32 }
+      - { name: g_nof_data, value: c_ddr_db_buf_nof_data }
+    mm_port_names:
+      - REG_DIAG_DATA_BUFFER_DDR_MB_II
+      - RAM_DIAG_DATA_BUFFER_DDR_MB_II
+
+  # JESD
+  - peripheral_name: tech_jesd204b/jesd_ctrl
+    mm_port_names:
+      - PIO_JESD_CTRL
+      
+  - peripheral_name: tech_jesd204b/jesd204b_arria10
+    parameter_overrides:
+      - { name: g_nof_streams, value: c_nof_streams_jesd204b }
+    mm_port_names:
+      - JESD204B
+
+  - peripheral_name: dp/dp_bsn_source
+    mm_port_names:
+      - REG_BSN_SOURCE
+
+  - peripheral_name: dp/dp_bsn_monitor
+    peripheral_group: input
+    parameter_overrides:
+      - { name: g_nof_streams, value: c_nof_streams_jesd204b }
+    mm_port_names:
+      - REG_BSN_MONITOR_INPUT
+
+  - peripheral_name: diag/diag_data_buffer
+    peripheral_group: bsn 
+    parameter_overrides:
+      - { name: g_nof_streams, value: c_nof_streams_jesd204b }
+      - { name: g_data_w, value: 16 }
+      - { name: g_nof_data, value: c_jesd_db_buf_nof_data }
+    mm_port_names:
+      - REG_DIAG_DATA_BUFFER_BSN
+      - RAM_DIAG_DATA_BUFFER_BSN

libraries/base/diag/diag.peripheral.yaml

@@ -97,5 +97,117 @@ peripherals:
               field_description: ""
               number_of_fields: g_nof_data
               address_offset: 0x0
-              mm_width: g_data_w
-              
+              user_width: g_data_w
+    
+  - peripheral_name: diag_block_gen    # pi_diag_block_gen.py
+    peripheral_description: "Block generator (BG)"
+    parameters:
+      # Parameters of mms_diag_block_gen.vhd
+      - { name: g_nof_streams, value: 1 }
+      - { name: g_buf_dat_w, value: 16 }
+      - { name: g_buf_addr_w, value: 7 }
+    mm_ports:
+      # MM port for mms_diag_block_gen.vhd
+      - mm_port_name: REG_DIAG_BG
+        mm_port_type: REG
+        mm_port_span: 8 * MM_BUS_SIZE
+        mm_port_description: "Block gen control."
+        number_of_mm_ports: 1
+        fields:
+          - - field_name: enable
+              address_offset: 0x0
+              bit_offset: 0
+              mm_width: 1
+          - - field_name: enable_sync
+              address_offset: 0x0
+              bit_offset: 1
+              mm_width: 1
+          - - field_name: samples_per_packet
+              address_offset: 0x4
+          - - field_name: blocks_per_sync
+              address_offset: 0x8
+          - - field_name: gapsize
+              address_offset: 0xc
+          - - field_name: mem_low_adrs
+              address_offset: 0x10
+          - - field_name: mem_high_adrs
+              address_offset: 0x14
+          - - field_name: bsn_init
+              address_offset: 0x18
+              user_width: 64
+              radix: uint64
+
+      # MM port for mms_diag_block_gen.vhd
+      - mm_port_name: RAM_DIAG_BG
+        mm_port_type: RAM
+        mm_port_span: ceil_pow2( 2**g_buf_addr_w * ceil_div(g_buf_dat_w, c_word_w)) * MM_BUS_SIZE
+        mm_port_description: "Block gen buffer memory, contains the data patterns to be generated."
+        number_of_mm_ports: g_nof_streams
+        fields:
+          - - field_name: data
+              field_description: ""
+              number_of_fields: 2**g_buf_addr_w
+              address_offset: 0x0
+              user_width: g_buf_dat_w        
+
+  - peripheral_name: diag_tx_seq    # pi_diag_tx_seq.py
+    peripheral_description: "TX test sequence"
+    parameters:
+      # Parameters of mms_diag_tx_seq.vhd
+      - { name: g_nof_streams, value: 1 }
+      - { name: g_mm_broadcast, value: False }
+    mm_ports:
+      # MM port for mms_diag_tx_seq.vhd
+      - mm_port_name: REG_DIAG_TX_SEQ
+        mm_port_type: REG
+        mm_port_span: 4 * MM_BUS_SIZE
+        mm_port_description: "TX test sequence control."
+        number_of_mm_ports: sel_a_b(g_mm_broadcast, 1, g_nof_streams)
+        fields:
+          - - field_name: control
+              address_offset: 0x0
+              mm_width: 3
+          - - field_name: init
+              address_offset: 0x4
+          - - field_name: tx_cnt
+              address_offset: 0x8
+              access_mode: RO
+          - - field_name: modulo
+              address_offset: 0xc
+
+  - peripheral_name: diag_rx_seq    # pi_diag_rx_seq.py
+    peripheral_description: "RX test sequence"
+    parameters:
+      # Parameters of mms_diag_rx_seq.vhd
+      - { name: g_nof_streams, value: 1 }
+    mm_ports:
+      # MM port for mms_diag_rx_seq.vhd
+      - mm_port_name: REG_DIAG_RX_SEQ
+        mm_port_type: REG
+        mm_port_span: 8 * MM_BUS_SIZE
+        mm_port_description: "RX test sequence control."
+        number_of_mm_ports: g_nof_streams
+        fields:
+          - - field_name: control
+              address_offset: 0x0
+              mm_width: 2
+          - - field_name: result
+              address_offset: 0x4
+              access_mode: RO
+              mm_width: 2
+          - - field_name: rx_cnt
+              address_offset: 0x8
+              access_mode: RO
+          - - field_name: rx_sample
+              address_offset: 0xc
+              access_mode: RO
+          - - field_name: step_0
+              address_offset: 0x10
+          - - field_name: step_1
+              address_offset: 0x14
+          - - field_name: step_2
+              address_offset: 0x18
+          - - field_name: step_3
+              address_offset: 0x1c
+
+  

libraries/base/util/util.peripheral.yaml

+schema_name: args
+schema_version: 1.0
+schema_type: peripheral
+
+hdl_library_name: util
+hdl_library_description: "Util Heater."
+
+peripherals:
+  - peripheral_name: heater    # pi_heater.py
+    peripheral_description: "Heater component, see util_heater.vhd"
+    mm_ports:
+      # MM port for util_heater.vhd
+      - mm_port_name: REG_HEATER
+        mm_port_type: REG
+        mm_port_span: 32 * MM_BUS_SIZE
+        mm_port_description: "Heater control."
+        fields:
+          - - field_name: enable
+              field_description: "Enable"
+              number_of_fields: 25
+              address_offset: 0x0
+
+

libraries/io/ddr/ddr.peripheral.yaml

+schema_name: args
+schema_version: 1.0
+schema_type: peripheral
+
+hdl_library_name: ddr 
+hdl_library_description: "Double data rate memory"
+
+peripherals:
+  - peripheral_name: io_ddr    # pi_io_ddr.py
+    peripheral_description: "DDR controller"
+    mm_ports:
+      # MM port for io_ddr_reg.vhd
+      - mm_port_name: REG_IO_DDR
+        mm_port_type: REG
+        mm_port_span: 8 * MM_BUS_SIZE
+        mm_port_description: "DDR controller registers."
+        number_of_mm_ports: 1
+        fields:
+          - - field_name: burstbegin
+              address_offset: 0x0
+              access_mode: WO
+              mm_width: 1
+          - - field_name: wr_not_rd
+              address_offset: 0x4
+              access_mode: WO
+              mm_width: 1
+          - - field_name: done 
+              address_offset: 0x8
+              access_mode: RO
+              mm_width: 1
+          - - field_name: address
+              address_offset: 0x14
+              access_mode: WO
+          - - field_name: burstsize
+              address_offset: 0x18
+              access_mode: WO
+          - - field_name: flush
+              address_offset: 0x1c
+              mm_width: 1
+
+