Add and verify ctlr_nof_bytes_per_word field in reg_io_ddr.

libraries/io/ddr/ddr.peripheral.yaml

@@ -20,6 +20,7 @@ peripherals:
               field_description: |
                 "IO DDR status bits concatenated:
                  ddr_gigabytes[7:0] &
+                 ctlr_nof_bytes_per_word[7:0] &
                  ctlr_tech_mosi.wr & ctlr_tech_miso.rdval & ctlr_tech_miso.cal_fail      & ctlr_tech_miso.cal_ok &
                  ctlr_rst_out_i    & ctlr_wr_flush_en     & ctlr_tech_miso.waitrequest_n & ctlr_tech_miso.done"
               address_offset: 0 * MM_BUS_SIZE

libraries/io/ddr/src/vhdl/io_ddr.vhd

@@ -234,7 +234,9 @@ ARCHITECTURE str OF io_ddr IS
   CONSTANT c_wr_use_ctrl       : BOOLEAN := sel_a_b(g_wr_flush_mode="SOP", TRUE, FALSE);
   CONSTANT c_wr_fifo_use_ctrl  : BOOLEAN := c_wr_use_sync OR c_wr_use_ctrl;
   
-  CONSTANT c_ddr_gigabytes    : NATURAL := func_tech_ddr_module_size(g_tech_ddr);  -- units GiByte
+  CONSTANT c_ddr_gigabytes           : NATURAL := func_tech_ddr_module_size(g_tech_ddr);  -- units GiByte
+  CONSTANT c_ctlr_nof_bytes_per_word : NATURAL := func_tech_ddr_ctlr_ip_data_w(g_tech_ddr) / c_byte_w;  -- unit byte
+
   CONSTANT c_ctlr_address_w    : NATURAL := func_tech_ddr_ctlr_address_w(g_tech_ddr);
   CONSTANT c_ctlr_data_w       : NATURAL := func_tech_ddr_ctlr_data_w(g_tech_ddr);
   CONSTANT c_wr_fifo_depth     : NATURAL := g_wr_fifo_depth * (c_ctlr_data_w/g_wr_data_w);  -- get FIFO depth at write side
@@ -522,6 +524,7 @@ BEGIN
                    RESIZE_UVEC(ctlr_wr_fifo_usedw, c_mem_reg_dat_w) & 
                    RESIZE_UVEC(ctlr_rd_fifo_usedw, c_mem_reg_dat_w) & 
                    RESIZE_UVEC(TO_UVEC(c_ddr_gigabytes, 8) &
+                               TO_UVEC(c_ctlr_nof_bytes_per_word, 8) &
                                ctlr_tech_mosi.wr & ctlr_tech_miso.rdval & ctlr_tech_miso.cal_fail      & ctlr_tech_miso.cal_ok &
                                ctlr_rst_out_i    & ctlr_wr_flush_en     & ctlr_tech_miso.waitrequest_n & ctlr_tech_miso.done, c_mem_reg_dat_w);   
   

libraries/io/ddr/tb/vhdl/tb_io_ddr.vhd

@@ -73,6 +73,7 @@ ARCHITECTURE str of tb_io_ddr IS
   CONSTANT c_tech_ddr                 : t_c_tech_ddr := func_tech_sel_ddr(g_sim_model, c_sim_ddr, c_mem_ddr);
   
   CONSTANT c_exp_gigabytes            : NATURAL := func_tech_ddr_module_size(c_tech_ddr);
+  CONSTANT c_exp_nof_bytes_per_word   : NATURAL := func_tech_ddr_ctlr_ip_data_w(c_tech_ddr) / c_byte_w;
 
   CONSTANT c_dp_clk_period            : TIME := 5 ns;   -- 200 MHz
   CONSTANT c_mm_clk_period            : TIME := 8 ns;   -- 125 MHz
@@ -167,6 +168,8 @@ ARCHITECTURE str of tb_io_ddr IS
   SIGNAL dbg_c_tech_ddr               : t_c_tech_ddr := c_tech_ddr;
   SIGNAL dbg_c_exp_gigabytes          : NATURAL := c_exp_gigabytes;  -- = 0 for sim model, else nof GB
   SIGNAL ddr_gigabytes                : NATURAL;
+  SIGNAL dbg_c_exp_nof_bytes_per_word : NATURAL := c_exp_nof_bytes_per_word;
+  SIGNAL ctlr_nof_bytes_per_word      : NATURAL;
   SIGNAL dbg_c_dp_data_w              : NATURAL := c_dp_data_w;
   SIGNAL dbg_c_wr_fifo_depth          : NATURAL := c_wr_fifo_depth;
   SIGNAL dbg_c_rd_fifo_depth          : NATURAL := c_rd_fifo_depth;
@@ -266,13 +269,18 @@ BEGIN
     -- Wait until calibration done (and ctlr_rst released)
     proc_common_wait_until_high(dvr_clk, dvr_done);
     
-    -- Read DDR4 memory size
+    -- Read DDR4 memory status
     proc_common_wait_cross_clock_domain_latency(mm_clk, dp_clk);
     proc_mem_mm_bus_rd(0, mm_clk, reg_io_ddr_miso, reg_io_ddr_mosi);
     proc_mem_mm_bus_rd_latency(1, mm_clk);
-    ddr_gigabytes <= TO_UINT(reg_io_ddr_miso.rddata(15 DOWNTO 8));
+    -- . verify ddr_gigabytes
+    ddr_gigabytes <= TO_UINT(reg_io_ddr_miso.rddata(23 DOWNTO 16));
     proc_common_wait_some_cycles(mm_clk, 1);
-    ASSERT ddr_gigabytes = c_exp_gigabytes REPORT "Wrong read memory size" SEVERITY ERROR;
+    ASSERT ddr_gigabytes = c_exp_gigabytes REPORT "Wrong read ddr_gigabytes" SEVERITY ERROR;
+    -- . verify ctlr_nof_bytes_per_word
+    ctlr_nof_bytes_per_word  <= TO_UINT(reg_io_ddr_miso.rddata(15 DOWNTO 8));
+    proc_common_wait_some_cycles(mm_clk, 1);
+    ASSERT ctlr_nof_bytes_per_word = c_exp_nof_bytes_per_word REPORT "Wrong read ctlr_nof_bytes_per_word" SEVERITY ERROR;
 
     -- Start diagnostics source for write and sink for verify read
     proc_common_wait_some_cycles(dp_clk, 1);