-Updated Description comment block with SOP/EOP feature.

libraries/technology/transceiver/sim_transceiver_serializer.vhd

@@ -26,25 +26,18 @@
 --   Basic serializer model for fast transceiver simulation
 -- Description:
 --   The model serializes parallel data using 10 serial bits per byte. The two 
---   extra bits are used to transfer (XGMII) control. The model can represent
---   any real transceiver encoding scheme (10b/8b, 66b/64b) because it the
---   modelled line rate does not have to be the same as the true line rate.
+--   extra bits are used to transfer control (valid, SOP/EOP).
+--   The model can represent any real transceiver encoding scheme (10b/8b, 66b/64b) 
+--   because the modelled line rate does not have to be the same as the true line rate.
 --   The key feature that the model provides is that the parallel data gets
 --   transported via a single 1-bit lane. This allows fast simulation of the 
---   link using the true port widths. The model also assumes that the
---   transceivers on both sides of the link use the same tr_clk. Therefore any
---   delay on the link must be an integer number of tr_clk cycles.
---   This model can be connected to the transmitter entity serial transmitter
---   output in simulation. As all serializers in the simualation are
---   simultaneously released from reset and share the same transceiver
---   reference clock, we don't need to worry about synchronization and can
---   simply assign one or more bits per serial group as validity indicator. The
---   most straightforward is to mimic 10/8 encoding for as far as data rates
+--   link using the true port widths.
+--   The most straightforward is to mimic 10/8 encoding for as far as data rates
 --   and clock ratios are concerned (not the encoding itself):
 --   * User data rate = (8/10)*line data rate
 --   * User clock frequency = User data rate / user data width
 --   * Serial data block size = 10 bits [9..0] LSb sent first
---     *  [9] = Unused, '0'., indiced by 'x' (so 9/8 encoding would suffice too).
+--     *  [9] = SOP/EOP; '1'=SOP;'U'=EOP.
 --     *  [8] = Control bit.
 --     *  [7..0] = Data
 --   * Word/byte alignment is not required because reference clk and rst are
@@ -59,7 +52,7 @@
 --               _ . . _ . . . . . . _ . . . . . . . . . _ . . . . . . . . . _ . . . . . . . . . _ .        
 -- tx_serial_out .|___|.|___________|.|_________________|.|_________________|.|_________________|.|_
 --              
---               c x 0 1 2 3 4 5 6 7 c x 0 1 2 3 4 5 6 7 c x 0 1 2 3 4 5 6 7 c x 0 1 2 3 4 5 6 7 c x
+--               c P 0 1 2 3 4 5 6 7 c P 0 1 2 3 4 5 6 7 c P 0 1 2 3 4 5 6 7 c P 0 1 2 3 4 5 6 7 c P
 --                  |<----- Byte 0 ---->|<----- Byte 1 ---->|<----- Byte 2 ---->|<----- Byte 3 ---->|
 --
 -- Remarks: