Apply wait between tb_end and ASSERT FAILURE.

libraries/technology/mac_10g/tb_tech_mac_10g_simulation_end.vhd

@@ -57,6 +57,7 @@ BEGIN
     
     -- Stop the simulation
     tb_end <= '1';
+    proc_common_wait_some_cycles(clk, 1);
     IF g_tb_end=FALSE THEN
       REPORT "Tb simulation finished." SEVERITY NOTE;
     ELSE