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Commit 4bb16a0f authored by Jonathan Hargreaves's avatar Jonathan Hargreaves
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IP for unb2b FPGA Arria 10 version e1sg

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libraries/technology/ip_arria10_e1sg/clkbuf_global/generate_ip.sh 0 → 100755
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#!/bin/bash
# -------------------------------------------------------------------------- #
#
# Copyright (C) 2014
# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
# -------------------------------------------------------------------------- #
#
# Purpose: Generate IP with Qsys
# Description:
# Generate the IP in a separate generated/ subdirectory.
#
# Usage:
#
# ./generate_ip.sh
#
# Tool settings for selected target "unb2" with arria10
. ${RADIOHDL}/tools/quartus/set_quartus unb2b
#qsys-generate --help
# Only generate the source IP
# - use --synthesis=VHDL to have top level in VHDL similar as with MegaWizard
qsys-generate ip_arria10_e1sg_clkbuf_global.qsys \
--synthesis=VHDL \
--simulation=VHDL \
--output-directory=generated \
--allow-mixed-language-simulation
libraries/technology/ip_arria10_e1sg/clkbuf_global/hdllib.cfg 0 → 100644
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hdl_lib_name = ip_arria10_e1sg_clkbuf_global
hdl_library_clause_name = ip_arria10_e1sg_clkbuf_global_altclkctrl_151
hdl_lib_uses_synth =
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e1sg
synth_files =
test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
$RADIOHDL/libraries/technology/ip_arria10_e1sg/clkbuf_global/compile_ip.tcl
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e1sg_clkbuf_global.qip
libraries/technology/ip_arria10_e1sg/clkbuf_global/ip_arria10_e1sg_clkbuf_global.qsys 0 → 100644
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<?xml version="1.0" encoding="UTF-8"?>
<system name="ip_arria10_e1sg_clkbuf_global">
<component
name="$${FILENAME}"
displayName="$${FILENAME}"
version="1.0"
description=""
tags="INTERNAL_COMPONENT=true"
categories="System"
tool="QsysStandard" />
<parameter name="bonusData"><![CDATA[bonusData
{
element altclkctrl_0
{
datum _sortIndex
{
value = "0";
type = "int";
}
}
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
<parameter name="device" value="10AX115S2F45E1SG" />
<parameter name="deviceFamily" value="Arria 10" />
<parameter name="deviceSpeedGrade" value="1" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="hideFromIPCatalog" value="true" />
<parameter name="lockedInterfaceDefinition" value="" />
<parameter name="maxAdditionalLatency" value="1" />
<parameter name="projectName" value="" />
<parameter name="sopcBorderPoints" value="false" />
<parameter name="systemHash" value="0" />
<parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
<connPtSystemInfos/>
</systemInfosDefinition>]]></parameter>
<parameter name="testBenchDutName" value="" />
<parameter name="timeStamp" value="0" />
<parameter name="useTestBenchNamingPattern" value="false" />
<instanceScript></instanceScript>
<interface
name="altclkctrl_input"
internal="altclkctrl_0.altclkctrl_input"
type="conduit"
dir="end">
<port name="inclk" internal="inclk" />
</interface>
<interface
name="altclkctrl_output"
internal="altclkctrl_0.altclkctrl_output"
type="conduit"
dir="end">
<port name="outclk" internal="outclk" />
</interface>
<module
name="altclkctrl_0"
kind="altclkctrl"
version="16.0"
enabled="1"
autoexport="1">
<parameter name="CLOCK_TYPE" value="1" />
<parameter name="DEVICE_FAMILY" value="Arria 10" />
<parameter name="ENA_REGISTER_MODE" value="1" />
<parameter name="GUI_USE_ENA" value="false" />
<parameter name="NUMBER_OF_CLOCKS" value="1" />
<parameter name="USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION" value="false" />
</module>
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
<interconnectRequirement for="$system" name="qsys_mm.enableEccProtection" value="FALSE" />
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
</system>
libraries/technology/ip_arria10_e1sg/complex_mult/README.txt 0 → 100644
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README.txt for $RADIOHDL/libraries/technology/ip_arria10/complex_mult
1) Porting
2) IP component
3) Compilation, simulation and verification
4) Synthesis
5) Remarks
1) Porting
The complex_mult IP was ported manually from Quartus v11.1 for Stratix IV to Quartus 15.0 for Arria10 by creating it in Qsys using
the same parameter settings.
2) IP component
The generated IP is not kept in SVN, only the Qsys source file:
ip_arria10_complex_mult.qsys
Therefore first the IP needs to be generated using:
./generate_ip.sh
3) Compilation, simulation and verification
The generated IP also contains a msim_setup.tcl file that was used to manually create:
compile_ip.tcl
This compile_ip.tcl is in the hdllib.cfg and gets compiled before the other code.
4) Synthesis
No synthesis trials were done, because this will implicitely be done when the IP is used in a design. The QIP file:
generated/ip_arria10_complex_mult.qip
is included in the hdllib.cfg and contains what is needed to synthesize the IP.
5) Remarks
a) Use generated IP specific library clause name
The generated ip_arria10_<lib_name>.vhd uses an IP specific library name. Therefore the hdllib.cfg uses the IP
specific library as library clause name to make it known:
hdl_lib_name = ip_arria10_<lib_name>
hdl_library_clause_name = ip_arria10_<lib_name>_<ip_specific>
\ No newline at end of file
libraries/technology/ip_arria10_e1sg/complex_mult/generate_ip.sh 0 → 100755
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#!/bin/bash
# -------------------------------------------------------------------------- #
#
# Copyright (C) 2014
# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
# -------------------------------------------------------------------------- #
#
# Purpose: Generate IP with Qsys
# Description:
# Generate the IP in a separate generated/ subdirectory.
#
# Usage:
#
# ./generate_ip.sh
#
# Tool settings for selected target "unb2" with arria10
. ${RADIOHDL}/tools/quartus/set_quartus unb2b
#qsys-generate --help
# Only generate the source IP
# - use --synthesis=VHDL to have top level in VHDL similar as with MegaWizard
qsys-generate ip_arria10_e1sg_complex_mult.qsys \
--synthesis=VHDL \
--simulation=VHDL \
--output-directory=generated \
--allow-mixed-language-simulation
libraries/technology/ip_arria10_e1sg/complex_mult/hdllib.cfg 0 → 100644
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hdl_lib_name = ip_arria10_e1sg_complex_mult
hdl_library_clause_name = ip_arria10_e1sg_complex_mult_altmult_complex_150
hdl_lib_uses_synth =
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e1sg
synth_files =
test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
$RADIOHDL/libraries/technology/ip_arria10_e1sg/complex_mult/compile_ip.tcl
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e1sg_complex_mult.qip
libraries/technology/ip_arria10_e1sg/complex_mult/ip_arria10_e1sg_complex_mult.qsys 0 → 100644
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<?xml version="1.0" encoding="UTF-8"?>
<system name="ip_arria10_e1sg_complex_mult">
<component
name="$${FILENAME}"
displayName="$${FILENAME}"
version="1.0"
description=""
tags="INTERNAL_COMPONENT=true"
categories="System"
tool="QsysStandard" />
<parameter name="bonusData"><![CDATA[bonusData
{
element altmult_complex_0
{
datum _sortIndex
{
value = "0";
type = "int";
}
}
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
<parameter name="device" value="10AX115S2F45E1SG" />
<parameter name="deviceFamily" value="Arria 10" />
<parameter name="deviceSpeedGrade" value="1" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="hideFromIPCatalog" value="true" />
<parameter name="lockedInterfaceDefinition" value="" />
<parameter name="maxAdditionalLatency" value="1" />
<parameter name="projectName" value="" />
<parameter name="sopcBorderPoints" value="false" />
<parameter name="systemHash" value="0" />
<parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
<connPtSystemInfos/>
</systemInfosDefinition>]]></parameter>
<parameter name="testBenchDutName" value="" />
<parameter name="timeStamp" value="0" />
<parameter name="useTestBenchNamingPattern" value="false" />
<instanceScript></instanceScript>
<interface
name="complex_input"
internal="altmult_complex_0.complex_input"
type="conduit"
dir="end">
<port name="aclr" internal="aclr" />
<port name="clock" internal="clock" />
<port name="dataa_imag" internal="dataa_imag" />
<port name="dataa_real" internal="dataa_real" />
<port name="datab_imag" internal="datab_imag" />
<port name="datab_real" internal="datab_real" />
<port name="ena" internal="ena" />
</interface>
<interface
name="complex_output"
internal="altmult_complex_0.complex_output"
type="conduit"
dir="end">
<port name="result_imag" internal="result_imag" />
<port name="result_real" internal="result_real" />
</interface>
<module
name="altmult_complex_0"
kind="altmult_complex"
version="16.0"
enabled="1"
autoexport="1">
<parameter name="CBX_AUTO_BLACKBOX" value="ALL" />
<parameter name="DEVICE_FAMILY" value="Arria 10" />
<parameter name="GUI_CLEAR_TYPE" value="ACLR" />
<parameter name="GUI_DYNAMIC_COMPLEX" value="false" />
<parameter name="GUI_USE_CLKEN" value="true" />
<parameter name="IMPLEMENTATION_STYLE" value="AUTO" />
<parameter name="PIPELINE" value="3" />
<parameter name="REPRESENTATION_A" value="1" />
<parameter name="REPRESENTATION_B" value="1" />
<parameter name="WIDTH_A" value="18" />
<parameter name="WIDTH_B" value="18" />
<parameter name="WIDTH_RESULT" value="36" />
</module>
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
<interconnectRequirement for="$system" name="qsys_mm.enableEccProtection" value="FALSE" />
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
</system>
libraries/technology/ip_arria10_e1sg/ddio/README.txt 0 → 100755
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README.txt for $RADIOHDL/libraries/technology/ip_arria10/ddio
Contents:
1) DDIO components
2) Arria10 IP
3) Synthesis trials
4) Issues
1) DDIO components:
ip_arria10_ddio_in.vhd = Double Date Rate input
ip_arria10_ddio_out.vhd = Double Date Rate output
2) Arria10 IP
The StratixIV IP uses altddio_in and altddio_out. First a Megawizard file for this StratixIV IP was made using the settings that
were used in common_ddio_in.vhd and common_ddio_out.vhd. This Megawizard IP file was then opened in Quartus to be able to let
Quartus 14 convert them using the altera_gpio component for Arria10.
The altera_gpio component is not part of the default Quartus 14.0a10 tool libraries, but instead it is created by Qsys together
with the IP. This makes that the altera_gpio can not easily be used in simulation and synthesis like was possible with altera_mf
in for Stratix IV (Quartus 11.1).
The ddio_in component is used by the PPSH and the ddio_out component is used by the ADUH. In both cases the g_width=1.
The Arria10 IP can be generated using a fixed width of 1. Therefore the width was set to 1 in the conversion from MegaWizard
to Qsys and the qsys files are stored as:
ip_arria10_ddio_in_1.qsys
ip_arria10_ddio_out_1.qsys
If the application would need a wider port then it can achieve this by instantiating the IP multiple times. This approach
avoids having to generate DDIO IP for every possible width. An alternative would be:
- to generate IP for e.g. width=16 and assuming that that is sufficient for all applications. Any application that uses less
width then leaves these IO unconnected so that the unused IO will get optimized away by synthesis.
- create the IP when it is needed, this scheme is more difficult to manage but is something to consider for the future.
The IP needs to be generated with:
./generate_ip.sh
to create the simulation and synthesis files, because these are initially not kept in SVN.
3) Synthesis trials
The Quartus project:
quartus/ddio.qpf
was used to verify that the DDIO IP actually synthesise to the appropriate FPGA resources.
Use the Quartus GUI to manually select a top level component for synthesis e.g. by right clicking the entity vhd file
in the file tab of the Quartus project navigator window.
Then check the resource usage in the synthesis and fitter reports.
4) Issues
a) Simulation model does not work (for Quartus 14.1, not tried for Quartus 15.0)
The simulation model for the DDIO does not compile ok because a din port is missing in the ddio_out en a dout port is
missing in the ddio_in. Adding this ports manualy does work for compile, but when the component is loaded as a simulation
then Modelsim reports some internal error on the IP. The compile also does not work when using 'do msim_setup.tcl', so
there is something wrong with the DDIO simulation model. The synthesis of the DDIO IP using ddio.qpf does work.
The work around is not not use the simulation model, but instead use a behavioral simulation model for the IP:
sim/ip_arria10_ddio_in_1.vhd
sim/ip_arria10_ddio_out_1.vhd
sim/tb_ip_arria10_ddio_1.vhd = self checking tb for ip_arria10_ddio_in_1 -> ip_arria10_ddio_out_1
The selection between the IP model or the behavioral model is made in the compile_ip.tcl script.
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#!/bin/bash
# -------------------------------------------------------------------------- #
#
# Copyright (C) 2014
# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
# -------------------------------------------------------------------------- #
#
# Purpose: Generate IP with Qsys
# Description:
# Generate the IP in a separate generated/ subdirectory.
#
# Remark:
#
# Usage:
#
# ./generate_ip.sh
#
#
# Tool settings for selected target "unb2" with arria10
. ${RADIOHDL}/tools/quartus/set_quartus unb2b
#qsys-generate --help
# Only generate the source IP
qsys-generate ip_arria10_e1sg_ddio_in_1.qsys --synthesis=VHDL --simulation=VHDL --output-directory=generated
qsys-generate ip_arria10_e1sg_ddio_out_1.qsys --synthesis=VHDL --simulation=VHDL --output-directory=generated
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hdl_lib_name = ip_arria10_e1sg_ddio
hdl_library_clause_name = ip_arria10_e1sg_ddio_lib
hdl_lib_uses_synth = technology
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e1sg
synth_files =
ip_arria10_e1sg_ddio_in.vhd
ip_arria10_e1sg_ddio_out.vhd
test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
$RADIOHDL/libraries/technology/ip_arria10_e1sg/ddio/compile_ip.tcl
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e1sg_ddio_in_1.qip
generated/ip_arria10_e1sg_ddio_out_1.qip
libraries/technology/ip_arria10_e1sg/ddio/ip_arria10_e1sg_ddio_in.vhd 0 → 100644
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-------------------------------------------------------------------------------
--
-- Copyright (C) 2014
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
-- Purpose: Wrapper for ip_arria10_e1sg_ddio_in_1 to support g_width >= 1
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY ip_arria10_e1sg_ddio_in IS
GENERIC (
g_width : NATURAL := 1
);
PORT (
in_dat : IN STD_LOGIC_VECTOR(g_width-1 DOWNTO 0);
in_clk : IN STD_LOGIC;
in_clk_en : IN STD_LOGIC := '1'; -- Not Connected
rst : IN STD_LOGIC := '0';
out_dat_hi : OUT STD_LOGIC_VECTOR(g_width-1 DOWNTO 0);
out_dat_lo : OUT STD_LOGIC_VECTOR(g_width-1 DOWNTO 0)
);
END ip_arria10_e1sg_ddio_in;
ARCHITECTURE str OF ip_arria10_e1sg_ddio_in IS
component ip_arria10_e1sg_ddio_in_1 is
port (
datain : in std_logic_vector(0 downto 0) := (others => '0'); -- pad_in.export
inclock : in std_logic := '0'; -- ck.export
aclr : in std_logic := '0'; -- aclr.export
dataout_h : out std_logic_vector(0 downto 0); -- dataout_h.fragment
dataout_l : out std_logic_vector(0 downto 0) -- dataout_l.fragment
);
end component;
BEGIN
gen_w : FOR I IN g_width-1 DOWNTO 0 GENERATE
u_ip_arria10_e1sg_ddio_in_1 : ip_arria10_e1sg_ddio_in_1
PORT MAP (
datain => in_dat(I DOWNTO I),
inclock => in_clk,
aclr => rst,
dataout_h => out_dat_hi(I DOWNTO I),
dataout_l => out_dat_lo(I DOWNTO I)
);
END GENERATE;
END str;
libraries/technology/ip_arria10_e1sg/ddio/ip_arria10_e1sg_ddio_in_1.qsys 0 → 100644
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<?xml version="1.0" encoding="UTF-8"?>
<system name="ip_arria10_e1sg_ddio_in_1">
<component
name="$${FILENAME}"
displayName="$${FILENAME}"
version="1.0"
description=""
tags=""
categories="System"
tool="QsysStandard" />
<parameter name="bonusData"><![CDATA[bonusData
{
element ip_arria10_ddio_in_1
{
datum _sortIndex
{
value = "0";
type = "int";
}
}
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
<parameter name="device" value="10AX115S2F45E1SG" />
<parameter name="deviceFamily" value="Arria 10" />
<parameter name="deviceSpeedGrade" value="1" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="hideFromIPCatalog" value="false" />
<parameter name="lockedInterfaceDefinition" value="" />
<parameter name="maxAdditionalLatency" value="1" />
<parameter name="projectName" value="" />
<parameter name="sopcBorderPoints" value="false" />
<parameter name="systemHash" value="0" />
<parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
<connPtSystemInfos/>
</systemInfosDefinition>]]></parameter>
<parameter name="testBenchDutName" value="" />
<parameter name="timeStamp" value="0" />
<parameter name="useTestBenchNamingPattern" value="false" />
<instanceScript></instanceScript>
<interface
name="aclr"
internal="ip_arria10_ddio_in_1.aclr"
type="conduit"
dir="end">
<port name="aclr" internal="aclr" />
</interface>
<interface name="ck" internal="ip_arria10_ddio_in_1.ck" type="conduit" dir="end">
<port name="inclock" internal="inclock" />
</interface>
<interface
name="dataout_h"
internal="ip_arria10_ddio_in_1.dataout_h"
type="conduit"
dir="end">
<port name="dataout_h" internal="dataout_h" />
</interface>
<interface
name="dataout_l"
internal="ip_arria10_ddio_in_1.dataout_l"
type="conduit"
dir="end">
<port name="dataout_l" internal="dataout_l" />
</interface>
<interface name="din" internal="ip_arria10_ddio_in_1.din" />
<interface name="dout" internal="ip_arria10_ddio_in_1.dout" />
<interface
name="pad_in"
internal="ip_arria10_ddio_in_1.pad_in"
type="conduit"
dir="end">
<port name="datain" internal="datain" />
</interface>
<interface name="pad_out" internal="ip_arria10_ddio_in_1.pad_out" />
<module
name="ip_arria10_ddio_in_1"
kind="altera_gpio"
version="16.0"
enabled="1"
autoexport="1">
<parameter name="AUTO_DEVICE" value="10AX115S2F45E1SG" />
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="1" />
<parameter name="EXT_DRIVER_PARAM" value="false" />
<parameter name="GENERATE_SDC_FILE" value="false" />
<parameter name="IP_MIGRATE_PORT_MAP_FILE">altddio_in_port_map.csv</parameter>
<parameter name="PIN_TYPE_GUI" value="Input" />
<parameter name="SIZE" value="1" />
<parameter name="device_family" value="Arria 10" />
<parameter name="gui_areset_mode" value="Clear" />
<parameter name="gui_bus_hold" value="false" />
<parameter name="gui_diff_buff" value="false" />
<parameter name="gui_enable_cke" value="false" />
<parameter name="gui_enable_migratable_port_names" value="true" />
<parameter name="gui_enable_termination_ports" value="false" />
<parameter name="gui_hr_logic" value="false" />
<parameter name="gui_io_reg_mode" value="DDIO" />
<parameter name="gui_open_drain" value="false" />
<parameter name="gui_pseudo_diff" value="false" />
<parameter name="gui_separate_io_clks" value="false" />
<parameter name="gui_sreset_mode" value="None" />
<parameter name="gui_use_oe" value="false" />
</module>
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
</system>
libraries/technology/ip_arria10_e1sg/ddio/ip_arria10_e1sg_ddio_out.vhd 0 → 100644
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-------------------------------------------------------------------------------
--
-- Copyright (C) 2014
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
-- Purpose: Wrapper for ip_arria10_e1sg_ddio_out_1 to support g_width >= 1
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY ip_arria10_e1sg_ddio_out IS
GENERIC(
g_width : NATURAL := 1
);
PORT (
rst : IN STD_LOGIC := '0';
in_clk : IN STD_LOGIC;
in_clk_en : IN STD_LOGIC := '1'; -- Not Connected
in_dat_hi : IN STD_LOGIC_VECTOR(g_width-1 DOWNTO 0);
in_dat_lo : IN STD_LOGIC_VECTOR(g_width-1 DOWNTO 0);
out_dat : OUT STD_LOGIC_VECTOR(g_width-1 DOWNTO 0)
);
END ip_arria10_e1sg_ddio_out;
ARCHITECTURE str OF ip_arria10_e1sg_ddio_out IS
component ip_arria10_e1sg_ddio_out_1 is
port (
dataout : out std_logic_vector(0 downto 0); -- pad_out.export
outclock : in std_logic := '0'; -- ck.export
aclr : in std_logic := '0'; -- aclr.export
datain_h : in std_logic_vector(0 downto 0) := (others => '0'); -- datain_h.fragment
datain_l : in std_logic_vector(0 downto 0) := (others => '0') -- datain_l.fragment
);
end component;
BEGIN
gen_w : FOR I IN g_width-1 DOWNTO 0 GENERATE
u_ip_arria10_e1sg_ddio_out_1 : ip_arria10_e1sg_ddio_out_1
PORT MAP (
dataout => out_dat(I DOWNTO I),
outclock => in_clk,
aclr => rst,
datain_h => in_dat_hi(I DOWNTO I),
datain_l => in_dat_lo(I DOWNTO I)
);
END GENERATE;
END str;
libraries/technology/ip_arria10_e1sg/ddio/ip_arria10_e1sg_ddio_out_1.qsys 0 → 100644
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<?xml version="1.0" encoding="UTF-8"?>
<system name="ip_arria10_e1sg_ddio_out_1">
<component
name="$${FILENAME}"
displayName="$${FILENAME}"
version="1.0"
description=""
tags=""
categories="System"
tool="QsysStandard" />
<parameter name="bonusData"><![CDATA[bonusData
{
element ip_arria10_ddio_out_1
{
datum _sortIndex
{
value = "0";
type = "int";
}
}
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
<parameter name="device" value="10AX115S2F45E1SG" />
<parameter name="deviceFamily" value="Arria 10" />
<parameter name="deviceSpeedGrade" value="1" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="hideFromIPCatalog" value="false" />
<parameter name="lockedInterfaceDefinition" value="" />
<parameter name="maxAdditionalLatency" value="1" />
<parameter name="projectName" value="" />
<parameter name="sopcBorderPoints" value="false" />
<parameter name="systemHash" value="0" />
<parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
<connPtSystemInfos/>
</systemInfosDefinition>]]></parameter>
<parameter name="testBenchDutName" value="" />
<parameter name="timeStamp" value="0" />
<parameter name="useTestBenchNamingPattern" value="false" />
<instanceScript></instanceScript>
<interface
name="aclr"
internal="ip_arria10_ddio_out_1.aclr"
type="conduit"
dir="end">
<port name="aclr" internal="aclr" />
</interface>
<interface
name="ck"
internal="ip_arria10_ddio_out_1.ck"
type="conduit"
dir="end">
<port name="inclock" internal="inclock" />
</interface>
<interface
name="datain_h"
internal="ip_arria10_ddio_out_1.datain_h"
type="conduit"
dir="end">
<port name="datain_h" internal="datain_h" />
</interface>
<interface
name="datain_l"
internal="ip_arria10_ddio_out_1.datain_l"
type="conduit"
dir="end">
<port name="datain_l" internal="datain_l" />
</interface>
<interface name="din" internal="ip_arria10_ddio_out_1.din" />
<interface
name="pad_out"
internal="ip_arria10_ddio_out_1.pad_out"
type="conduit"
dir="end">
<port name="dataout" internal="dataout" />
</interface>
<module
name="ip_arria10_ddio_out_1"
kind="altera_gpio"
version="16.0"
enabled="1"
autoexport="1">
<parameter name="AUTO_DEVICE" value="10AX115S2F45E1SG" />
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="1" />
<parameter name="EXT_DRIVER_PARAM" value="false" />
<parameter name="GENERATE_SDC_FILE" value="false" />
<parameter name="IP_MIGRATE_PORT_MAP_FILE">altddio_out_port_map.csv</parameter>
<parameter name="PIN_TYPE_GUI" value="Output" />
<parameter name="SIZE" value="1" />
<parameter name="device_family" value="Arria 10" />
<parameter name="gui_areset_mode" value="Clear" />
<parameter name="gui_bus_hold" value="false" />
<parameter name="gui_diff_buff" value="false" />
<parameter name="gui_enable_cke" value="false" />
<parameter name="gui_enable_migratable_port_names" value="true" />
<parameter name="gui_enable_termination_ports" value="false" />
<parameter name="gui_hr_logic" value="false" />
<parameter name="gui_io_reg_mode" value="DDIO" />
<parameter name="gui_open_drain" value="false" />
<parameter name="gui_pseudo_diff" value="false" />
<parameter name="gui_separate_io_clks" value="false" />
<parameter name="gui_sreset_mode" value="None" />
<parameter name="gui_use_oe" value="false" />
</module>
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
</system>
libraries/technology/ip_arria10_e1sg/ddio/sim/ip_arria10_e1sg_ddio_in_1.vhd 0 → 100644
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-------------------------------------------------------------------------------
--
-- Copyright (C) 2014
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
-- Purpose: Simulation model for DDIO in
-- Description:
-- The double data rate datain samples that arrive at time series t0, t1, t2,
-- ... get output with samples t0, t2, ... in dataout_l and samples t1, t3,
-- ... in dataout_h. Hence dataout = dataout_h & dataout_l contains the
-- time series samples in little endian format with the first sample in the
-- LSpart as shown in the timing diagram:
-- _ _ _ _
-- inclock | |_| |_| |_| |_
-- datain 0 1 2 3 4 5 6 7
-- in_dat_r 1 3 5
-- in_dat_f 0 2 4
-- dataout_h 1 3 5
-- dataout_l 0 2 4
--
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY ip_arria10_e1sg_ddio_in_1 IS
PORT (
datain : IN STD_LOGIC_VECTOR(0 downto 0) := (others => '0');
inclock : IN STD_LOGIC := '0';
aclr : IN STD_LOGIC := '0';
dataout_h : OUT STD_LOGIC_VECTOR(0 downto 0);
dataout_l : OUT STD_LOGIC_VECTOR(0 downto 0)
);
END ip_arria10_e1sg_ddio_in_1;
ARCHITECTURE beh OF ip_arria10_e1sg_ddio_in_1 IS
SIGNAL in_dat_r : STD_LOGIC;
SIGNAL in_dat_f : STD_LOGIC;
BEGIN
in_dat_r <= datain(0) WHEN rising_edge(inclock);
in_dat_f <= datain(0) WHEN falling_edge(inclock);
dataout_h <= (OTHERS=>in_dat_r);
dataout_l <= (OTHERS=>in_dat_f) WHEN rising_edge(inclock);
END beh;
libraries/technology/ip_arria10_e1sg/ddio/sim/ip_arria10_e1sg_ddio_out_1.vhd 0 → 100644
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-------------------------------------------------------------------------------
--
-- Copyright (C) 2014
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
-- Purpose: Simulation model for DDIO out
-- Description:
-- This function is the inverse of DDIO in as described in ip_arria10_e1sg_ddio_in_1.
-- The timing diagram:
-- _ _ _ _ _
-- outclock | |_| |_| |_| |_| |_
-- datain_h 1 3 5
-- datain_l 0 2 4
-- dataout @ r 1 3 5
-- dataout @ f 0 2 4
-- dataout 0 1 2 3 4 5 6 7
--
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY ip_arria10_e1sg_ddio_out_1 IS
PORT (
dataout : OUT STD_LOGIC_VECTOR(0 downto 0);
outclock : IN STD_LOGIC := '0';
aclr : IN STD_LOGIC := '0';
datain_h : IN STD_LOGIC_VECTOR(0 downto 0) := (others=>'0');
datain_l : IN STD_LOGIC_VECTOR(0 downto 0) := (others=>'0')
);
END ip_arria10_e1sg_ddio_out_1;
ARCHITECTURE beh OF ip_arria10_e1sg_ddio_out_1 IS
SIGNAL out_dat_r : STD_LOGIC;
SIGNAL out_dat_f : STD_LOGIC;
BEGIN
dataout <= datain_l WHEN falling_edge(outclock) ELSE
datain_h WHEN rising_edge(outclock);
END beh;
libraries/technology/ip_arria10_e1sg/ddio/sim/tb_ip_arria10_e1sg_ddio_1.vhd 0 → 100644
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-------------------------------------------------------------------------------
--
-- Copyright (C) 2014
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
-- Purpose: Test bench for the DDIO in and out simulation models
-- Description:
-- _ _ _ _
-- inclock | |_| |_| |_| |_
-- datain 0 1 2 3 4 5 6 7
-- data_h 1 3 5
-- data_l 0 2 4
-- dataout 0 1 2 3 4 5 6 7
--
-- Usage:
-- The tb is self checking (p_verify) and self stopping (tb_end)
--
-- . Load the simulation by right mouse selecting the entity in library work
-- > as 3
-- > run -a
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY tb_ip_arria10_e1sg_ddio_1 IS
END tb_ip_arria10_e1sg_ddio_1;
ARCHITECTURE tb OF tb_ip_arria10_e1sg_ddio_1 IS
CONSTANT c_clk_period : TIME := 10 ns;
SIGNAL tb_end : STD_LOGIC := '0';
SIGNAL clk : STD_LOGIC := '1';
SIGNAL in_dat : STD_LOGIC;
SIGNAL in_data : STD_LOGIC_VECTOR(0 DOWNTO 0);
SIGNAL data_h : STD_LOGIC_VECTOR(0 DOWNTO 0);
SIGNAL data_l : STD_LOGIC_VECTOR(0 DOWNTO 0);
SIGNAL out_data : STD_LOGIC_VECTOR(0 DOWNTO 0);
SIGNAL out_dat : STD_LOGIC;
SIGNAL out_dat_exp : STD_LOGIC;
BEGIN
tb_end <= '0', '1' AFTER 100*c_clk_period;
clk <= NOT clk OR tb_end AFTER c_clk_period/2;
p_in : PROCESS
BEGIN
-- 0
in_dat <= '0';
WAIT UNTIL falling_edge(clk);
in_dat <= '0';
WAIT UNTIL rising_edge(clk);
-- 1
in_dat <= '0';
WAIT UNTIL falling_edge(clk);
in_dat <= '1';
WAIT UNTIL rising_edge(clk);
-- 2
in_dat <= '1';
WAIT UNTIL falling_edge(clk);
in_dat <= '0';
WAIT UNTIL rising_edge(clk);
-- 3
in_dat <= '1';
WAIT UNTIL falling_edge(clk);
in_dat <= '1';
WAIT UNTIL rising_edge(clk);
-- 2
in_dat <= '1';
WAIT UNTIL falling_edge(clk);
in_dat <= '0';
WAIT UNTIL rising_edge(clk);
END PROCESS;
in_data(0) <= in_dat;
u_ddio_in : ENTITY work.ip_arria10_e1sg_ddio_in_1
PORT MAP (
datain => in_data,
inclock => clk,
dataout_h => data_h,
dataout_l => data_l
);
u_ddio_out : ENTITY work.ip_arria10_e1sg_ddio_out_1
PORT MAP (
dataout => out_data,
outclock => clk,
datain_h => data_h,
datain_l => data_l
);
out_dat <= out_data(0);
out_dat_exp <= TRANSPORT in_dat AFTER c_clk_period*1.5 + 1 ps;
p_verify : PROCESS(clk)
BEGIN
IF falling_edge(clk) THEN
ASSERT out_dat=out_dat_exp REPORT "tb_ip_arria10_e1sg_ddio_1: Error, unexpeced data at falling edge";
END IF;
IF rising_edge(clk) THEN
ASSERT out_dat=out_dat_exp REPORT "tb_ip_arria10_e1sg_ddio_1: Error, unexpeced data at rising edge";
END IF;
END PROCESS;
END tb;
libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/copy_hex_files.tcl 0 → 100644
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#------------------------------------------------------------------------------
#
# Copyright (C) 2015
# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
#------------------------------------------------------------------------------
# This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
file copy -force $IP_DIR/../altera_emif_arch_nf_151/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_151_4thorvi_seq_cal_sim.hex ./
file copy -force $IP_DIR/../altera_emif_arch_nf_151/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_151_4thorvi_seq_cal_synth.hex ./
file copy -force $IP_DIR/../altera_emif_arch_nf_151/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_151_4thorvi_seq_params_sim.hex ./
file copy -force $IP_DIR/../altera_emif_arch_nf_151/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_151_4thorvi_seq_params_synth.hex ./
}
libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generate_ip.sh 0 → 100755
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#!/bin/bash
# -------------------------------------------------------------------------- #
#
# Copyright (C) 2014
# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
# -------------------------------------------------------------------------- #
#
# Purpose: Generate IP with Qsys
# Description:
# Generate the IP in a separate generated/ subdirectory.
#
# Usage:
#
# ./generate_ip.sh
#
# Tool settings for selected target "unb2" with arria10
. ${RADIOHDL}/tools/quartus/set_quartus unb2b
#qsys-generate --help
# Only generate the source IP
# - use --synthesis=VHDL to have top level in VHDL similar as with MegaWizard
qsys-generate ip_arria10_e1sg_ddr4_4g_1600.qsys \
--synthesis=VHDL \
--simulation=VHDL \
--output-directory=generated \
--allow-mixed-language-simulation
# Also generate the testbench IP, this is not useful because it only generates bus functional models, so not a DDR4 memory model
#qsys-generate ip_arria10_e1sg_ddr4_4g_1600.qsys \
# --synthesis=VHDL \
# --simulation=VHDL \
# --testbench=STANDARD \
# --testbench-simulation=VHDL \
# --output-directory=generated \
# --allow-mixed-language-simulation \
# --allow-mixed-language-testbench-simulation
libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/hdllib.cfg 0 → 100644
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− 0
View file @ 4bb16a0f
hdl_lib_name = ip_arria10_e1sg_ddr4_4g_1600
hdl_library_clause_name = ip_arria10_e1sg_ddr4_4g_1600_altera_emif_151
hdl_lib_uses_synth =
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e1sg
synth_files =
test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
$RADIOHDL/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/compile_ip.tcl
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e1sg_ddr4_4g_1600.qip
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