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707481b3

Commit 707481b3 authored 9 years ago by Jonathan Hargreaves

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IP for dual rank DDR4 module (8GB) based on ~/altera_designs/ddr4_rev7 (MbI...

IP for dual rank DDR4 module (8GB) based on ~/altera_designs/ddr4_rev7 (MbI version, may also work on mbII)

parent e8eb599f

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libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/compile_ip.tcl 65 additions, 0 deletions

.../technology/ip_arria10_e3sge3/ddr4_8g_1600/compile_ip.tcl
libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/copy_hex_files.tcl 33 additions, 0 deletions

...hnology/ip_arria10_e3sge3/ddr4_8g_1600/copy_hex_files.tcl
libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/generate_ip.sh 54 additions, 0 deletions

.../technology/ip_arria10_e3sge3/ddr4_8g_1600/generate_ip.sh
libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/hdllib.cfg 16 additions, 0 deletions

...ries/technology/ip_arria10_e3sge3/ddr4_8g_1600/hdllib.cfg
libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/ip_arria10_e3sge3_ddr4_8g_1600.qsys 1077 additions, 0 deletions

...0_e3sge3/ddr4_8g_1600/ip_arria10_e3sge3_ddr4_8g_1600.qsys

with 1245 additions and 0 deletions

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