Added regression_test_vhdl key plus some tb.

libraries/technology/eth_10g/hdllib.cfg

@@ -16,6 +16,8 @@ test_bench_files =
     tb_tech_eth_10g_ppm.vhd
     tb_tb_tech_eth_10g.vhd
     
+regression_test_vhdl = 
+    tb_tb_tech_eth_10g.vhd
 
 [modelsim_project_file]
 

libraries/technology/eth_10g/tb_tb_tech_eth_10g.vhd

@@ -45,6 +45,7 @@ ARCHITECTURE tb OF tb_tb_tech_eth_10g IS
   
   CONSTANT c_tb_end_vec : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS=>'1');
   SIGNAL   tb_end_vec   : STD_LOGIC_VECTOR(7 DOWNTO 0) := c_tb_end_vec;  -- sufficiently long to fit all tb instances
+  SIGNAL   tb_end       : STD_LOGIC := '0';
   
 BEGIN
 
@@ -62,9 +63,12 @@ BEGIN
   u_tech_eth_10g : ENTITY work.tb_tech_eth_10g GENERIC MAP (c_tech_select_default, FALSE, FALSE, 0, c_644, c_156, c_data_type, TRUE, FALSE) PORT MAP (tb_end_vec(1));
   u_sim_eth_10g  : ENTITY work.tb_tech_eth_10g GENERIC MAP (c_tech_select_default, FALSE, FALSE, 1, c_644, c_156, c_data_type, TRUE, FALSE) PORT MAP (tb_end_vec(2));
   
+  tb_end <= '1' WHEN tb_end_vec=c_tb_end_vec ELSE '0';
+  
   p_tb_end : PROCESS
   BEGIN
-    WAIT UNTIL tb_end_vec=c_tb_end_vec;
+    WAIT UNTIL tb_end='1';
+    WAIT FOR 1 ns;
     REPORT "Multi tb simulation finished." SEVERITY FAILURE;
     WAIT;
   END PROCESS;

libraries/technology/transceiver/hdllib.cfg

@@ -21,6 +21,9 @@ synth_files =
 test_bench_files =
     tb_sim_transceiver_serdes.vhd
 
+regression_test_vhdl = 
+    tb_sim_transceiver_serdes.vhd
+
 
 [modelsim_project_file]
 

libraries/technology/tse/hdllib.cfg

@@ -20,6 +20,9 @@ test_bench_files =
     tb_tech_tse_pkg.vhd
     tb_tech_tse.vhd
 
+regression_test_vhdl = 
+    tb_tech_tse.vhd
+
 
 [modelsim_project_file]
 

libraries/technology/tse/tb_tech_tse.vhd

@@ -83,6 +83,7 @@ ARCHITECTURE tb OF tb_tech_tse IS
   SIGNAL total_header_etherlen   : t_network_total_header;
   
   -- Clocks and reset
+  SIGNAL rx_end            : STD_LOGIC := '0';
   SIGNAL tb_end            : STD_LOGIC := '0';
   SIGNAL eth_clk           : STD_LOGIC := '0';  -- tse reference clock
   SIGNAL sys_clk           : STD_LOGIC := '0';  -- system clock
@@ -187,7 +188,7 @@ BEGIN
     END LOOP;
 
     FOR I IN 0 TO 1500 * 2 LOOP WAIT UNTIL rising_edge(st_clk); END LOOP;
-    tb_end <= '1';
+    rx_end <= '1';
     WAIT;
   END PROCESS;
 
@@ -256,10 +257,9 @@ BEGIN
   tx_pkt_cnt <= tx_pkt_cnt + 1 WHEN tx_sosi.sop='1' AND rising_edge(st_clk);
   rx_pkt_cnt <= rx_pkt_cnt + 1 WHEN rx_sosi.eop='1' AND rising_edge(st_clk);
   
-  p_tb_end : PROCESS  
+  p_verify : PROCESS
   BEGIN
-    WAIT UNTIL tb_end='1';
-    
+    WAIT UNTIL rx_end='1';
     -- Verify that all transmitted packets have been received
     IF tx_pkt_cnt=0 THEN
       REPORT "No packets were transmitted." SEVERITY ERROR;
@@ -268,9 +268,15 @@ BEGIN
     ELSIF tx_pkt_cnt/=rx_pkt_cnt THEN
       REPORT "Not all transmitted packets were received." SEVERITY ERROR;
     END IF;
+    tb_end <= '1';
+    WAIT;
+  END PROCESS;
   
-    -- Stop the simulation
-    ASSERT FALSE REPORT "Simulation finished." SEVERITY FAILURE;
+  p_tb_end : PROCESS  
+  BEGIN
+    WAIT UNTIL tb_end='1';
+    WAIT FOR 1 ns;
+    REPORT "Simulation finished." SEVERITY FAILURE;
     WAIT;
   END PROCESS;