Commits · e05e39801c9d47b48ca8e2b3591e6acb1d417629 · RTSD / HDL

Oct 06, 2015
- added the 10G transceivers for 48 channels per ATXPLL · e05e3980
  Kenneth Hiemstra authored 9 years ago
  
  e05e3980
- -Re-commit as the last one appeared to have failed. · 91b1d3b9
  Daniel van der Schuur authored 9 years ago
  
  91b1d3b9
Oct 05, 2015
- cosmetic · e259607f
  Kenneth Hiemstra authored 9 years ago
  
  e259607f
Oct 02, 2015
- -Fixed MM bus address widths. · aa9c138b
  Daniel van der Schuur authored 9 years ago
  
  aa9c138b
Oct 01, 2015
- connected the fpga_temp_sensor to common_reg_r_w_dc, available for MM · 63966715
  Kenneth Hiemstra authored 9 years ago
  
  readout
  63966715
- update · 1a94194a
  Kenneth Hiemstra authored 9 years ago
  
  1a94194a
- added the library for the fpga temp sensor · 17594f25
  Kenneth Hiemstra authored 9 years ago
  
  17594f25
- added the tech_ layer for the fpga temp sensor · 40dafeee
  Kenneth Hiemstra authored 9 years ago
  
  40dafeee
- added the fpga temp sensor for arria10 · 010771fc
  Kenneth Hiemstra authored 9 years ago
  
  010771fc
- fixed DDR3 IP for 16GB SO-Dimms · aa76980d
  Zanting authored 9 years ago
  
  aa76980d
Sep 30, 2015
- Changed default to stratixiv · 5adcb3c8
  Zanting authored 9 years ago
  
  5adcb3c8
- Reverted to own pll/dll for 4g single rank slave · 16a4215a
  Zanting authored 9 years ago
  
  16a4215a
- Reverted to own pll/dll for 4g single rank slave · cde216f4
  Zanting authored 9 years ago
  
  cde216f4
- IP for 16GB DDR3 So-Dimm modules added · 878ceca5
  Zanting authored 9 years ago
  
  878ceca5
- IP for 16GB DDR3 So-Dimm modules added · 4750ad20
  Zanting authored 9 years ago
  
  4750ad20
Sep 29, 2015
- Added files for mixed radix fft in configuration file · 1906bc71
  Comore authored 9 years ago
  
  1906bc71
Sep 28, 2015
- IP for 16GB DDR3 So-Dimm modules added · 67c8bcec
  Zanting authored 9 years ago
  
  67c8bcec
- added DDR4 doc for IP generation · 1ddc8157
  Kenneth Hiemstra authored 9 years ago
  
  1ddc8157
- IP for 16GB DDR3 So-Dimm modules · cace6663
  Zanting authored 9 years ago
  
  cace6663
Sep 25, 2015
- fixed magic codes · 5d9e7979
  Kenneth Hiemstra authored 9 years ago
  
  5d9e7979
- cosmetic · db950540
  Kenneth Hiemstra authored 9 years ago
  
  db950540
- can choose now ddr4 1600 or 2000 · fda9eccc
  Kenneth Hiemstra authored 9 years ago
  
  fda9eccc
Sep 24, 2015
- Updated DDR3 slave IP · 428bf5d7
  Zanting authored 9 years ago
  
  428bf5d7
- -Removed MM control bus; · d0a5694a
  Daniel van der Schuur authored 9 years ago
  
  -Changed architecture (not the function).
  d0a5694a
- -updated dp_offload_tx instance · ccc62067
  Daniel van der Schuur authored 9 years ago
  
  ccc62067
- -Stripped down the design; · 12121667
  Daniel van der Schuur authored 9 years ago
  
  -Updated port map to updated dp_offload_tx (not committed yet).
  12121667
Sep 22, 2015
- Added generic for bypassing the prefilter. · 85100936
  Pepping authored 9 years ago
  
  85100936
Sep 15, 2015
- Force eth1g_ram_mosi bus to reset state in order to remove annoying warning... · 80a453ea
  Dumez authored 9 years ago
  
  Force eth1g_ram_mosi bus to reset state in order to remove annoying warning messages during simulation
  80a453ea
Sep 11, 2015
- added gluelogic for the 4x chan 10G IPs · 16ff9a6d
  Kenneth Hiemstra authored 9 years ago
  
  16ff9a6d
- added possible 10G channel configs · c066bd8f
  Kenneth Hiemstra authored 9 years ago
  
  c066bd8f
Sep 09, 2015
- deleted because correct name is ip_arria10_pll_xgmii_mac_clocks.qsys · c63d6b56
  Kenneth Hiemstra authored 9 years ago
  
  c63d6b56
Sep 04, 2015
- -Copied dp_stream_player.vhd to RadioHDL. · c5fb84fc
  Daniel van der Schuur authored 9 years ago
  
  c5fb84fc
- -Restored g_blk_sync in mms_diag_block_gen.vhd as it is required for · 193e31d9
  Daniel van der Schuur authored 9 years ago
  
  rsp_terminal_frame_gen.vhd.
  193e31d9
Aug 29, 2015
- moved to ATXPLL driving 12 PHY's instead of 24 · e1e5d150
  Kenneth Hiemstra authored 9 years ago
  
  e1e5d150
- moved to ATXPLL driving 12 PHY's instead of 24 · c80abada
  Kenneth Hiemstra authored 9 years ago
  
  c80abada
Aug 18, 2015
- changed the ATXPLL selecting from 1-24 to 1-12. Either 1 ATXPLL will · aaf62b8f
  Kenneth Hiemstra authored 9 years ago
  
  drive 1xPHY or 1 ATXPLL will drive 12xPHY (recommented by Altera)
  aaf62b8f
- added ddr4_4g_2000 IP · 08d9a16e
  Kenneth Hiemstra authored 9 years ago
  
  08d9a16e
- 10G PHY. 12 channels driven by 1 ATXPLL · 7620fd87
  Kenneth Hiemstra authored 9 years ago
  
  7620fd87
- based on ddr4_4g_1600 but changed clock/timings · dcf1dc3b
  Kenneth Hiemstra authored 9 years ago
  
  dcf1dc3b
Aug 17, 2015
- Reverted edit in path · 45ef5f3e
  Pepping authored 9 years ago
  
  45ef5f3e