added the fpga temp sensor for arria10

libraries/technology/ip_arria10/temp_sense/compile_ip.tcl

+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10/temp_sense/generated/sim"
+
+#vlib ./work/         ;# Assume library work already exists
+
+vmap ip_arria10_temp_sense_altera_temp_sense_150 ./work/
+
+  vcom "$IP_DIR/ip_arria10_temp_sense.vhd"
+

libraries/technology/ip_arria10/temp_sense/generate_ip.sh

+#!/bin/bash
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2014                                                        
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>           
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands                             
+#                                                                           
+# This program is free software: you can redistribute it and/or modify      
+# it under the terms of the GNU General Public License as published by      
+# the Free Software Foundation, either version 3 of the License, or         
+# (at your option) any later version.                                       
+#                                                                           
+# This program is distributed in the hope that it will be useful,           
+# but WITHOUT ANY WARRANTY; without even the implied warranty of            
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the             
+# GNU General Public License for more details.                              
+#                                                                           
+# You should have received a copy of the GNU General Public License         
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.     
+#
+# -------------------------------------------------------------------------- #
+#
+# Purpose: Generate IP with Qsys
+# Description:
+#   Generate the IP in a separate generated/ subdirectory.
+#
+# Usage:
+#
+#   ./generate_ip.sh
+#
+
+# Tool settings for selected target "unb2" with arria10
+. ${RADIOHDL}/tools/quartus/set_quartus unb2
+
+#qsys-generate --help
+
+# Only generate the source IP
+# - use --synthesis=VHDL to have top level in VHDL similar as with MegaWizard
+qsys-generate ip_arria10_temp_sense.qsys \
+              --synthesis=VHDL \
+              --simulation=VHDL \
+              --output-directory=generated \
+              --allow-mixed-language-simulation

libraries/technology/ip_arria10/temp_sense/hdllib.cfg

+hdl_lib_name = ip_arria10_temp_sense 
+hdl_library_clause_name = ip_arria10_temp_sense_altera_temp_sense_150
+hdl_lib_uses_synth = 
+hdl_lib_uses_sim = 
+
+hdl_lib_technology = ip_arria10
+
+modelsim_compile_ip_files =
+    $RADIOHDL/libraries/technology/ip_arria10/temp_sense/compile_ip.tcl
+
+synth_files =
+    
+test_bench_files = 
+
+quartus_qip_files = generated/ip_arria10_temp_sense.qip

libraries/technology/ip_arria10/temp_sense/ip_arria10_temp_sense.qsys

+<?xml version="1.0" encoding="UTF-8"?>
+<system name="$${FILENAME}">
+ <component
+   name="$${FILENAME}"
+   displayName="$${FILENAME}"
+   version="1.0"
+   description=""
+   tags="INTERNAL_COMPONENT=true"
+   categories="System" />
+ <parameter name="bonusData"><![CDATA[bonusData 
+{
+   element $${FILENAME}
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element temp_sense_0
+   {
+      datum _sortIndex
+      {
+         value = "0";
+         type = "int";
+      }
+   }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="10AX115S4F45I3SGES" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="3" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="maxAdditionalLatency" value="1" />
+ <parameter name="projectName" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+   name="corectl"
+   internal="temp_sense_0.corectl"
+   type="conduit"
+   dir="end">
+  <port name="corectl" internal="corectl" />
+ </interface>
+ <interface name="eoc" internal="temp_sense_0.eoc" type="conduit" dir="end">
+  <port name="eoc" internal="eoc" />
+ </interface>
+ <interface name="reset" internal="temp_sense_0.reset" type="conduit" dir="end">
+  <port name="reset" internal="reset" />
+ </interface>
+ <interface
+   name="tempout"
+   internal="temp_sense_0.tempout"
+   type="conduit"
+   dir="end">
+  <port name="tempout" internal="tempout" />
+ </interface>
+ <module
+   name="temp_sense_0"
+   kind="altera_temp_sense"
+   version="15.0"
+   enabled="1"
+   autoexport="1">
+  <parameter name="CBX_AUTO_BLACKBOX" value="ALL" />
+  <parameter name="CE_CHECK" value="false" />
+  <parameter name="CLK_FREQUENCY" value="1.0" />
+  <parameter name="CLOCK_DIVIDER_VALUE" value="40" />
+  <parameter name="CLR_CHECK" value="false" />
+  <parameter name="DEVICE_FAMILY" value="Arria 10" />
+  <parameter name="NUMBER_OF_SAMPLES" value="128" />
+  <parameter name="POI_CAL_TEMPERATURE" value="85" />
+  <parameter name="SIM_TSDCALO" value="0" />
+  <parameter name="USER_OFFSET_ENABLE" value="off" />
+  <parameter name="USE_WYS" value="on" />
+ </module>
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
+</system>