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RTSD
HDL
Commits
16a4215a
Commit
16a4215a
authored
9 years ago
by
Zanting
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Reverted to own pll/dll for 4g single rank slave
parent
cde216f4
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libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave.v
+92
-96
92 additions, 96 deletions
...0_slave/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave.v
with
92 additions
and
96 deletions
libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave.v
+
92
−
96
View file @
16a4215a
...
...
@@ -2,16 +2,16 @@
// GENERATION: XML
// ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave.v
// Generated using ACDS version 11.1sp2 259 at 2015.0
9.01
.15:0
7:56
// Generated using ACDS version 11.1sp2 259 at 2015.0
8.12
.15:0
0:22
`timescale
1
ps
/
1
ps
module
ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave
(
input
wire
pll_ref_clk
,
// pll_ref_clk.clk
input
wire
global_reset_n
,
// global_reset.reset_n
input
wire
soft_reset_n
,
// soft_reset.reset_n
in
put
wire
afi_clk
,
// afi_clk
_in
.clk
in
put
wire
afi_half_clk
,
// afi_half_clk
_in
.clk
in
put
wire
afi_reset_n
,
// afi_reset
_in
.reset_n
out
put
wire
afi_clk
,
// afi_clk.clk
out
put
wire
afi_half_clk
,
// afi_half_clk.clk
out
put
wire
afi_reset_n
,
// afi_reset.reset_n
output
wire
[
15
:
0
]
mem_a
,
// memory.mem_a
output
wire
[
2
:
0
]
mem_ba
,
// .mem_ba
output
wire
[
1
:
0
]
mem_ck
,
// .mem_ck
...
...
@@ -40,27 +40,25 @@ module ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave (
output
wire
local_init_done
,
// status.local_init_done
output
wire
local_cal_success
,
// .local_cal_success
output
wire
local_cal_fail
,
// .local_cal_fail
input
wire
oct_rdn
,
// oct.rdn
input
wire
oct_rup
,
// .rup
output
wire
[
13
:
0
]
seriesterminationcontrol
,
// oct_sharing.seriesterminationcontrol
output
wire
[
13
:
0
]
parallelterminationcontrol
,
// .parallelterminationcontrol
input
wire
pll_mem_clk
,
// pll_sharing.pll_mem_clk
input
wire
pll_write_clk
,
// .pll_write_clk
input
wire
pll_write_clk_pre_phy_clk
,
// .pll_write_clk_pre_phy_clk
input
wire
pll_addr_cmd_clk
,
// .pll_addr_cmd_clk
input
wire
pll_locked
,
// .pll_locked
input
wire
pll_avl_clk
,
// .pll_avl_clk
input
wire
pll_config_clk
,
// .pll_config_clk
input
wire
[
5
:
0
]
dll_delayctrl
// dll_sharing.dll_delayctrl
input
wire
[
13
:
0
]
seriesterminationcontrol
,
// oct_sharing.seriesterminationcontrol
input
wire
[
13
:
0
]
parallelterminationcontrol
,
// .parallelterminationcontrol
output
wire
pll_mem_clk
,
// pll_sharing.pll_mem_clk
output
wire
pll_write_clk
,
// .pll_write_clk
output
wire
pll_write_clk_pre_phy_clk
,
// .pll_write_clk_pre_phy_clk
output
wire
pll_addr_cmd_clk
,
// .pll_addr_cmd_clk
output
wire
pll_locked
,
// .pll_locked
output
wire
pll_avl_clk
,
// .pll_avl_clk
output
wire
pll_config_clk
,
// .pll_config_clk
output
wire
[
5
:
0
]
dll_delayctrl
// dll_sharing.dll_delayctrl
);
ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave_0002
ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave_inst
(
.
pll_ref_clk
(
pll_ref_clk
),
// pll_ref_clk.clk
.
global_reset_n
(
global_reset_n
),
// global_reset.reset_n
.
soft_reset_n
(
soft_reset_n
),
// soft_reset.reset_n
.
afi_clk
(
afi_clk
),
// afi_clk
_in
.clk
.
afi_half_clk
(
afi_half_clk
),
// afi_half_clk
_in
.clk
.
afi_reset_n
(
afi_reset_n
),
// afi_reset
_in
.reset_n
.
afi_clk
(
afi_clk
),
// afi_clk.clk
.
afi_half_clk
(
afi_half_clk
),
// afi_half_clk.clk
.
afi_reset_n
(
afi_reset_n
),
// afi_reset.reset_n
.
mem_a
(
mem_a
),
// memory.mem_a
.
mem_ba
(
mem_ba
),
// .mem_ba
.
mem_ck
(
mem_ck
),
// .mem_ck
...
...
@@ -89,8 +87,6 @@ module ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave (
.
local_init_done
(
local_init_done
),
// status.local_init_done
.
local_cal_success
(
local_cal_success
),
// .local_cal_success
.
local_cal_fail
(
local_cal_fail
),
// .local_cal_fail
.
oct_rdn
(
oct_rdn
),
// oct.rdn
.
oct_rup
(
oct_rup
),
// .rup
.
seriesterminationcontrol
(
seriesterminationcontrol
),
// oct_sharing.seriesterminationcontrol
.
parallelterminationcontrol
(
parallelterminationcontrol
),
// .parallelterminationcontrol
.
pll_mem_clk
(
pll_mem_clk
),
// pll_sharing.pll_mem_clk
...
...
@@ -321,9 +317,9 @@ endmodule
// Retrieval info: <generic name="HHP_REMAP_ADDR" value="true" />
// Retrieval info: <generic name="USE_SEQUENCER_APB_BRIDGE" value="false" />
// Retrieval info: <generic name="DEFAULT_FAST_SIM_MODEL" value="true" />
// Retrieval info: <generic name="PLL_SHARING_MODE" value="
Slave
" />
// Retrieval info: <generic name="DLL_SHARING_MODE" value="
Slave
" />
// Retrieval info: <generic name="OCT_SHARING_MODE" value="
Master
" />
// Retrieval info: <generic name="PLL_SHARING_MODE" value="
Master
" />
// Retrieval info: <generic name="DLL_SHARING_MODE" value="
Master
" />
// Retrieval info: <generic name="OCT_SHARING_MODE" value="
Slave
" />
// Retrieval info: <generic name="ABSTRACT_REAL_COMPARE_TEST" value="false" />
// Retrieval info: <generic name="INCLUDE_BOARD_DELAY_MODEL" value="false" />
// Retrieval info: <generic name="USE_FAKE_PHY" value="false" />
...
...
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