connected the fpga_temp_sensor to common_reg_r_w_dc, available for MM

readout

libraries/io/fpga_temp_sens/src/vhdl/fpga_temp_sens.vhd

@@ -76,43 +76,30 @@ BEGIN
       reset   => mm_rst,
       tempout => temp_data --: OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
     );
+
+    PROCESS(eoc, mm_rst)
+    BEGIN
+      IF mm_rst = '1' THEN
+        mm_reg_temp_data <= (OTHERS => '0');
+      ELSIF falling_edge(eoc) THEN
+        mm_reg_temp_data <= RESIZE_UVEC(temp_data,c_mem_reg_dat_w);
+      END IF;
+    END PROCESS;
+
   END GENERATE;
 
+
+
   gen_no_tech_fpga_temp_sens: IF g_sim = TRUE GENERATE
     temp_data <= RESIZE_UVEC(x"45",10);
+    mm_reg_temp_data <= RESIZE_UVEC(temp_data,c_mem_reg_dat_w);
   END GENERATE;
 
 
 
---
----- leon: work this out
---ENTITY register32 IS PORT(
---    d   : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
---    ld  : IN STD_LOGIC; -- load/enable.
---    clr : IN STD_LOGIC; -- async. clear.
---    clk : IN STD_LOGIC; -- clock.
---    q   : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) -- output
---);
---END register32;
---
---
---
---  process(clk, clr)
---    begin
---        if clr = '1' then
---            q <= x"00000000";
---        elsif rising_edge(clk) then
---            if ld = '1' then
---                q <= d;
---            end if;
---        end if;
---  end process;
----- leon: work this out
---
 
 
-  mm_reg_temp_data <= RESIZE_UVEC(temp_data,c_mem_reg_dat_w);
-  
+
 
   u_reg_map : ENTITY common_lib.common_reg_r_w_dc
   GENERIC MAP (