cosmetic

libraries/io/fpga_temp_sens/src/vhdl/fpga_temp_sens.vhd

@@ -65,7 +65,7 @@ ARCHITECTURE str OF fpga_temp_sens IS
 
 BEGIN
 
-  gen_tech_fpga_temp_sens: IF g_sim = FALSE GENERATE
+  gen_tech_fpga_temp_sens: IF g_sim=FALSE GENERATE
     u_tech_fpga_temp_sens : ENTITY tech_fpga_temp_sens_lib.tech_fpga_temp_sens
     GENERIC MAP (
       g_technology => g_technology
@@ -90,7 +90,7 @@ BEGIN
 
 
 
-  gen_no_tech_fpga_temp_sens: IF g_sim = TRUE GENERATE
+  gen_no_tech_fpga_temp_sens: IF g_sim=TRUE GENERATE
     temp_data <= RESIZE_UVEC(x"45",10);
     mm_reg_temp_data <= RESIZE_UVEC(temp_data,c_mem_reg_dat_w);
   END GENERATE;