added the library for the fpga temp sensor

libraries/io/fpga_temp_sens/hdllib.cfg

+hdl_lib_name = fpga_temp_sens
+hdl_library_clause_name = fpga_temp_sens_lib
+hdl_lib_uses_synth = common technology tech_fpga_temp_sens
+hdl_lib_uses_sim = 
+
+hdl_lib_technology = 
+
+synth_files =
+    src/vhdl/fpga_temp_sens.vhd
+
+test_bench_files = 
+

libraries/io/fpga_temp_sens/src/vhdl/fpga_temp_sens.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2015
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose:
+-- Description:
+--  
+
+
+LIBRARY IEEE, common_lib, technology_lib, tech_fpga_temp_sens_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
+--USE tech_temp_sense_lib.tech_temp_sense_component_pkg.ALL;
+
+
+ENTITY fpga_temp_sens IS
+  GENERIC (
+    g_technology     : NATURAL := c_tech_select_default;
+    g_sim            : BOOLEAN
+  );
+  PORT (
+    -- MM interface
+    mm_rst      : IN  STD_LOGIC;
+    mm_clk      : IN  STD_LOGIC;
+
+    start_sense : IN  STD_LOGIC;
+    
+    reg_mosi    : IN  t_mem_mosi := c_mem_mosi_rst;
+    reg_miso    : OUT t_mem_miso
+  );
+END fpga_temp_sens;
+
+
+ARCHITECTURE str OF fpga_temp_sens IS
+
+  CONSTANT c_mem_reg_adr_w     : NATURAL := 1;
+  CONSTANT c_mem_reg_dat_w     : NATURAL := 32;
+  CONSTANT c_mem_reg_nof_data  : NATURAL := 1;
+  CONSTANT c_mem_reg_temp_data : t_c_mem := (c_mem_reg_rd_latency, c_mem_reg_adr_w , c_mem_reg_dat_w , c_mem_reg_nof_data, 'X');
+
+  SIGNAL mm_reg_temp_data : STD_LOGIC_VECTOR(c_mem_reg_dat_w-1 downto 0);
+  SIGNAL temp_data        : STD_LOGIC_VECTOR(9 downto 0);
+  SIGNAL eoc              : STD_LOGIC;
+
+BEGIN
+
+  gen_tech_fpga_temp_sens: IF g_sim = FALSE GENERATE
+    u_tech_fpga_temp_sens : ENTITY tech_fpga_temp_sens_lib.tech_fpga_temp_sens
+    GENERIC MAP (
+      g_technology => g_technology
+    )
+    PORT MAP (
+      corectl => start_sense,
+      eoc     => eoc,      --: OUT STD_LOGIC;
+      reset   => mm_rst,
+      tempout => temp_data --: OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
+    );
+  END GENERATE;
+
+  gen_no_tech_fpga_temp_sens: IF g_sim = TRUE GENERATE
+    temp_data <= RESIZE_UVEC(x"45",10);
+  END GENERATE;
+
+
+
+--
+---- leon: work this out
+--ENTITY register32 IS PORT(
+--    d   : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+--    ld  : IN STD_LOGIC; -- load/enable.
+--    clr : IN STD_LOGIC; -- async. clear.
+--    clk : IN STD_LOGIC; -- clock.
+--    q   : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) -- output
+--);
+--END register32;
+--
+--
+--
+--  process(clk, clr)
+--    begin
+--        if clr = '1' then
+--            q <= x"00000000";
+--        elsif rising_edge(clk) then
+--            if ld = '1' then
+--                q <= d;
+--            end if;
+--        end if;
+--  end process;
+---- leon: work this out
+--
+
+
+  mm_reg_temp_data <= RESIZE_UVEC(temp_data,c_mem_reg_dat_w);
+  
+
+  u_reg_map : ENTITY common_lib.common_reg_r_w_dc
+  GENERIC MAP (
+    g_cross_clock_domain => FALSE,
+    g_in_new_latency     => 0,
+    g_readback           => FALSE,
+    g_reg                => c_mem_reg_temp_data,
+    g_init_reg           => (OTHERS => '0')
+  )
+  PORT MAP (
+    -- Clocks and reset
+    mm_rst      => mm_rst,
+    mm_clk      => mm_clk,
+    st_rst      => mm_rst,
+    st_clk      => mm_clk,
+
+    -- Memory Mapped Slave in mm_clk domain
+    sla_in      => reg_mosi,
+    sla_out     => reg_miso,
+
+    -- MM registers in st_clk domain
+    reg_wr_arr  => OPEN,
+    reg_rd_arr  => OPEN,
+    in_new      => '1',
+    in_reg      => mm_reg_temp_data,
+    out_reg     => OPEN
+  );
+END str;