added the tech_ layer for the fpga temp sensor

libraries/technology/fpga_temp_sens/hdllib.cfg

+hdl_lib_name = tech_fpga_temp_sens
+hdl_library_clause_name = tech_fpga_temp_sens_lib
+hdl_lib_uses_synth = technology common ip_arria10_temp_sense
+hdl_lib_uses_sim = 
+
+hdl_lib_technology = 
+
+synth_files =
+    tech_fpga_temp_sens_component_pkg.vhd
+    tech_fpga_temp_sens.vhd
+    
+test_bench_files =

libraries/technology/fpga_temp_sens/tech_fpga_temp_sens.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2015
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY ieee, technology_lib;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+--USE ip_arria10_temp_sense_altera_temp_sense_150.ip_arria10_temp_sense_pkg.all;
+USE work.tech_fpga_temp_sens_component_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
+
+LIBRARY ip_arria10_temp_sense_altera_temp_sense_150;
+
+
+ENTITY tech_fpga_temp_sens IS
+  GENERIC (
+    g_technology : NATURAL := c_tech_select_default
+  );
+	PORT (
+		corectl : IN  STD_LOGIC             := '0'; -- corectl.corectl
+		eoc     : OUT STD_LOGIC;                    --     eoc.eoc
+		reset   : IN  STD_LOGIC             := '0'; --   reset.reset
+		tempout : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)  -- tempout.tempout
+	);
+END tech_fpga_temp_sens;
+
+ARCHITECTURE str OF tech_fpga_temp_sens IS
+
+BEGIN
+  gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
+	  u0 : ip_arria10_temp_sense
+		PORT MAP (
+			corectl => corectl, -- corectl.corectl
+			reset   => reset,   --   reset.reset
+			tempout => tempout, -- tempout.tempout
+			eoc     => eoc      --     eoc.eoc
+		);
+  END GENERATE;
+
+END ARCHITECTURE;

libraries/technology/fpga_temp_sens/tech_fpga_temp_sens_component_pkg.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2015
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: IP components declarations for various devices that get wrapped by the tech components
+
+library IEEE;
+USE IEEE.std_logic_1164.ALL;
+
+PACKAGE tech_fpga_temp_sens_component_pkg IS
+
+  COMPONENT ip_arria10_temp_sense IS
+  	PORT (
+  		corectl : IN  STD_LOGIC := '0';            -- corectl.corectl
+  		eoc     : OUT STD_LOGIC;                   -- eoc.eoc
+  		reset   : IN  STD_LOGIC := '0';            -- reset.reset
+  		tempout : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) -- tempout.tempout
+  	);
+  END COMPONENT;
+
+END tech_fpga_temp_sens_component_pkg;
+