Commits · d52a9e8c16c87b6e9d408084cd53e4fc2af755b6 · RTSD / HDL · GitLab

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Jul 30, 2018
- added copy_hex_files.tcl for ip_arria10_e1sg · d52a9e8c
  Reinier van der Walle authored 6 years ago
  
  d52a9e8c
Dec 08, 2017
- Imporved g_sim_model description comment. · c8ebfe11
  Eric Kooistra authored 7 years ago
  
  c8ebfe11
Jun 13, 2017
- Fixed DDR simulation model. · a2f529f6
  Eric Kooistra authored 7 years ago
  
  a2f529f6
Mar 17, 2017
- Added proc_common_timeout_failure(). · d52574e6
  Eric Kooistra authored 8 years ago
  
  d52574e6
Oct 31, 2016
- Added extra register for rd_fifo_full bit and wr_fifo_full bit. · 7fb08f74
  Pepping authored 8 years ago
  
  7fb08f74
May 11, 2016
- Added regression_test_vhdl with tb. · 6faf1e4a
  Eric Kooistra authored 8 years ago
  
  6faf1e4a
- Use tb_end signal. · 5787dd18
  Eric Kooistra authored 8 years ago
  
  5787dd18
Apr 28, 2016
- Removed tech_ddr3 because it is unknown. · 506d8cea
  Eric Kooistra authored 9 years ago
  
  506d8cea
Apr 19, 2016
- Added [section headers]. · b232c8c7
  Eric Kooistra authored 9 years ago
  
  b232c8c7
Oct 18, 2015
- Added and pass on g_technology. · 9c281f47
  Eric Kooistra authored 9 years ago
  
  9c281f47
Jul 09, 2015
- Pass on ctlr_miso.done to wr_snk_out.xon to support XON flow control. · d48977ca
  Eric Kooistra authored 9 years ago
  
  d48977ca
Jun 30, 2015
- Removed clock period generics. Corrected c_ctlr_ref_clk_period = 25 MHz for DDR4. · 43931c4b
  Eric Kooistra authored 9 years ago
  
  43931c4b
Jun 26, 2015
- Use separate g_dp_wr_fifo_depth and g_dp_rd_fifo_depth. · fbadd894
  Eric Kooistra authored 9 years ago
  
  fbadd894
- Derive g_rd_fifo_af_margin internally in io_ddr.vhd based on g_tech_ddr.name=DDR3 or DDR4. · 12fd53ea
  Eric Kooistra authored 9 years ago
  
  12fd53ea
Jun 25, 2015
- Removed dvr_clk, because it is the mm_clk. Fixed use g_cross_domain_dvr_ctlr =... · 755f1acb
  Eric Kooistra authored 9 years ago
  755f1acb
- Used g_cross_domain_delay_len=c_meta_delay_len fixed instead of via generic. · a8775752
  Eric Kooistra authored 9 years ago
  
  a8775752
- Removed clock domain crossing logic for this control register, because that is... · edb2c90e
  Eric Kooistra authored 9 years ago
  edb2c90e
- Used g_cross_domain_delay_len=c_meta_delay_len fixed instead of via generic. · 298065ab
  Eric Kooistra authored 9 years ago
  
  298065ab
Jun 24, 2015
- Register ctlr_wr_flush_en to ease timing closure. · df1c1e28
  Eric Kooistra authored 9 years ago
  
  df1c1e28
Jun 12, 2015
- Added g_sim_model. · 33e83b5a
  Eric Kooistra authored 9 years ago
  
  33e83b5a
- Added g_sim_model. Renamed instances. · 0306fe4b
  Eric Kooistra authored 9 years ago
  
  0306fe4b
- Provide streaming access to IO_DDR using a Tx seq and a Rx seq with optional DB RAM. · 61f16974
  Eric Kooistra authored 9 years ago
  
  61f16974
Jun 11, 2015
- Added draft src/vhdl/mms_io_ddr_diag.vhd, it intstantiates the BG, DB and... · 4e1d928d
  Eric Kooistra authored 9 years ago
  4e1d928d
May 08, 2015
- Corrected asserting ctlr_mosi.burstbegin for only one clock cycle as specified... · bd490884
  Eric Kooistra authored 9 years ago
  bd490884
- Corrected use of ctrl_miso.waitrequest_n to avoid combinational loop with ctrl_mosi.wr and rd. · 5551601d
  Eric Kooistra authored 9 years ago
  
  5551601d
May 06, 2015
- -Added fast behavioural model to tech_ddr.vhd; · cb21fc96
  Daniel van der Schuur authored 9 years ago
  cb21fc96
Apr 23, 2015
- Initial commit · 6aeae2e5
  Pepping authored 10 years ago
  
  6aeae2e5
Apr 20, 2015
- Moves modelsim_search_libraries to hdltool_unb1.cfg. · dbaee060
  Eric Kooistra authored 10 years ago
  
  dbaee060
- Added io_ddr_reg and mms_io_ddr · 7986c083
  Pepping authored 10 years ago
  
  7986c083
Apr 17, 2015
- Moved build_dir_sim and build_dir_synth keys from local hdllib.cfg to central hdltool.cfg · 45a081e7
  Eric Kooistra authored 10 years ago
  
  45a081e7
Apr 15, 2015
- Fixed default value of wr_snk_out.xon to '1'. This fixes the DDR3 issue on hardware. · 4c5369bf
  Zanting authored 10 years ago
  
  4c5369bf
Apr 13, 2015
- Added more signals to register · e3bf0da1
  Pepping authored 10 years ago
  
  e3bf0da1
Apr 10, 2015
- Use default reg_io_ddr_mosi input value to allow not connecting it. · 7b7329ca
  Eric Kooistra authored 10 years ago
  
  7b7329ca
Apr 09, 2015
- - Added fifo used words to the register for both rd and wr fifo · 996114aa
  Pepping authored 10 years ago
  996114aa
Apr 08, 2015
- Added cal_fail and cal_ok to register · f1fd048b
  Pepping authored 10 years ago
  
  f1fd048b
- Removed internal DDR memory model (now needs to be instantiated in tb). Use... · 17ede428
  Eric Kooistra authored 10 years ago
  17ede428
- Removed g_use_ddr_memory_model so the DDR memory model code is not seen/needed... · d51f8638
  Eric Kooistra authored 10 years ago
  d51f8638
- Renamed ctlr_mosi into ctlr_tech_mosi for the technology IP side to more... · fe14a691
  Eric Kooistra authored 10 years ago
  fe14a691
- Added missing g_mm_clk_period = 8 ns. · fbd48441
  Eric Kooistra authored 10 years ago
  
  fbd48441
Mar 30, 2015
- Added register map in TB · fc4e910c
  Pepping authored 10 years ago
  
  fc4e910c