placed u_sim_model under gen_ddr3 such that it will not be used for DDR4 simulation, the sim_model does not work when simulating the testbench for unb2b

Removed g_use_ddr_memory_model so the DDR memory model code is not seen/needed by synthesis. Instead only support DDR memory model instantiation in test bench.

Improved stimuli using generics and functions to define the write and read block accesses. Distinghuis between tests for DDR3 and DDR4, because DDR4 model simulates about 20x slower.

Added g_sim, when TRUE then use internal DDR memory model in tech_ddr component. When FALSE use DDR memory model in test bench.

Added io_ddr_cross_domain.vhd to handle dvr_clk and ctlr_clk domains in case they are different clock domains.

Added tb_tb_tb_eth.vhd to simulate eth for multiple technologies (currently only stratixiv).

Added regression tbfor eth library. Still need to fix run -all, because due to sim FAILURE the sim already stops at the first tb that finishes.

- Use common_network_layers_pkg from common (was eth_layers in $UNB)
- Use tech_tse_pkg and tb_tech_tse_pkg from tech_tse_lib (was work=tse_lib in $UNB)

Use ip_<device name> directories instead of following the altera/altera_mf library namings.
Move all Altera IP for Stratix IV to ip_stratixiv/ and use prefix ip_stratixiv_<component_name> for the IP files.
Remove xilinx/xilinx_core directory. Instead added ip_virtex4/ directory with empty hdllib.cfg.

Ported common RAM, ROM components from /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk to /home/kooistra/svnroot/UniBoard_FP7/RadioHDL/trunk.