Commits · ae27c70ebed9463b381ddcf57223ea3cb7c06acc · RTSD / HDL · GitLab

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Jan 19, 2022
- Work around for verifying DDR4 on unb2c. · ae27c70e
  Eric Kooistra authored 3 years ago
  
  ae27c70e
Jul 31, 2018
- fixed the FIXME in io_ddr testbench · f9e6bc4b
  Reinier van der Walle authored 6 years ago
  
  f9e6bc4b
Jul 30, 2018
- placed u_sim_model under gen_ddr3 such that it will not be used for DDR4... · d2c123fa
  Reinier van der Walle authored 6 years ago
  d2c123fa
Jun 13, 2017
- Fixed DDR simulation model. · a2f529f6
  Eric Kooistra authored 7 years ago
  
  a2f529f6
Mar 17, 2017
- Added proc_common_timeout_failure(). · d52574e6
  Eric Kooistra authored 8 years ago
  
  d52574e6
May 11, 2016
- Use tb_end signal. · 5787dd18
  Eric Kooistra authored 9 years ago
  
  5787dd18
Jun 30, 2015
- Removed clock period generics. Corrected c_ctlr_ref_clk_period = 25 MHz for DDR4. · 43931c4b
  Eric Kooistra authored 9 years ago
  
  43931c4b
Jun 12, 2015
- Added g_sim_model. · 33e83b5a
  Eric Kooistra authored 9 years ago
  
  33e83b5a
Apr 08, 2015
- Removed g_use_ddr_memory_model so the DDR memory model code is not seen/needed... · d51f8638
  Eric Kooistra authored 10 years ago
  d51f8638
- Added missing g_mm_clk_period = 8 ns. · fbd48441
  Eric Kooistra authored 10 years ago
  
  fbd48441
Mar 25, 2015
- Renamed g_sim into g_use_ddr_memory_model. · 24cd1054
  Eric Kooistra authored 10 years ago
  
  24cd1054
Jan 23, 2015
- Defined u_default with typical parameters. · 3519269e
  Eric Kooistra authored 10 years ago
  
  3519269e
- Added g_rd_fifo_depth. · 6ed6463b
  Eric Kooistra authored 10 years ago
  
  6ed6463b
- Added u_wr_burst_size_1. · baf6c23f
  Eric Kooistra authored 10 years ago
  
  baf6c23f
Jan 22, 2015
- The DDR4 IP/mem model simulation about 40x slower than that for DDR3. · 1a9bb01b
  Eric Kooistra authored 10 years ago
  
  1a9bb01b
Jan 20, 2015
- Improved stimuli using generics and functions to define the write and read... · 9fed08ae
  Eric Kooistra authored 10 years ago
  9fed08ae
Jan 14, 2015
- Define g_tech_ddr as generic. · 5538bc02
  Eric Kooistra authored 10 years ago
  
  5538bc02
Jan 08, 2015
- Added g_sim, when TRUE then use internal DDR memory model in tech_ddr... · e8956d9d
  Eric Kooistra authored 10 years ago
  e8956d9d
Jan 06, 2015
- Define g_dp_data_w as generic to be able to select mixed width or equal width FIFO. · d1e0547b
  Eric Kooistra authored 10 years ago
  
  d1e0547b
Jan 05, 2015
- Added io_ddr_cross_domain.vhd to handle dvr_clk and ctlr_clk domains in case... · f52fc96d
  Eric Kooistra authored 10 years ago
  f52fc96d
- Added multi test bench · 49acc58d
  Eric Kooistra authored 10 years ago
  
  49acc58d
Dec 05, 2014
- Added tb/vhdl/tb_tb_tr_nonbonded.vhd. · 625a53eb
  Eric Kooistra authored 10 years ago
  
  625a53eb
Oct 08, 2014
- Added technology select support to test benches. · d384ccbb
  Eric Kooistra authored 10 years ago
  d384ccbb
Jul 21, 2014
- Added tb_tb_tb_unb1_board_regression.vhd with all self-checking tb. · b64c6a5b
  Eric Kooistra authored 10 years ago
  
  b64c6a5b
Jun 13, 2014
- Added regression tbfor eth library. Still need to fix run -all, because due to... · 9efd96a9
  Eric Kooistra authored 10 years ago
  9efd96a9
- Added description. · f3dc5d7c
  Eric Kooistra authored 10 years ago
  
  f3dc5d7c
Jun 12, 2014
- Ported tse/eth* in $UNB to io/eth/ in $RADIOHDL. · da5812ab
  Eric Kooistra authored 10 years ago
  da5812ab
Jun 05, 2014
- Moved technology_pkg.vhd and technology_select_pkg.vhd from base/ to . and remove base/. · 9c655ef0
  Eric Kooistra authored 10 years ago
  9c655ef0
May 27, 2014
- Ported common RAM, ROM components from... · 901887ef
  Eric Kooistra authored 10 years ago
  901887ef