drive 1xPHY or 1 ATXPLL will drive 12xPHY (recommented by Altera)

Updated all IP related files to match Quartus 15.0 which uses libraries with _150 in their names instead of -141.

(MCGB) (x6/xN)

Renamed key hdl_lib_uses into hdl_lib_uses_synth and added new key hdl_lib_uses_sim for extra test_bench_files library dependencies.

to quartus compile

Time tx_ready and rx_ready after tr_rst release. Otherwise tb_tb_tech_eth_10g u_sim misses the first packets.

Use fractional PLL to created 156.25 MHz and 312.5 MHz for mac_10g and for 10gbase_r. The 10gbase_r XGMII interface is not available at 32b so need to stick to 64b@ 156.25MHz.