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Commit 35cb7dd8 authored by Eric Kooistra's avatar Eric Kooistra
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Moved modelsim_search_libraries key to hdltool_<toolset>.cfg

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libraries/technology/10gbase_r/hdllib.cfg
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− 3
View file @ 35cb7dd8
...@@ -22,6 +22,3 @@ synth_files = ...@@ -22,6 +22,3 @@ synth_files =
test_bench_files = test_bench_files =
tb_tech_10gbase_r.vhd tb_tech_10gbase_r.vhd
modelsim_search_libraries =
altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver twentynm_ver twentynm_hssi_ver twentynm_hip_ver
altera lpm sgate altera_mf altera_lnsim twentynm twentynm_hssi twentynm_hip
libraries/technology/eth_10g/hdllib.cfg
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− 3
View file @ 35cb7dd8
...@@ -16,6 +16,3 @@ test_bench_files = ...@@ -16,6 +16,3 @@ test_bench_files =
tb_tech_eth_10g_ppm.vhd tb_tech_eth_10g_ppm.vhd
tb_tb_tech_eth_10g.vhd tb_tb_tech_eth_10g.vhd
modelsim_search_libraries =
altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver stratixiv_ver stratixiv_hssi_ver stratixiv_pcie_hip_ver twentynm_ver twentynm_hssi_ver twentynm_hip_ver
altera lpm sgate altera_mf altera_lnsim stratixiv stratixiv_hssi stratixiv_pcie_hip twentynm twentynm_hssi twentynm_hip
libraries/technology/ip_arria10/ddio/hdllib.cfg
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− 4
View file @ 35cb7dd8
...@@ -14,10 +14,6 @@ synth_files = ...@@ -14,10 +14,6 @@ synth_files =
test_bench_files = test_bench_files =
modelsim_search_libraries =
altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver twentynm_ver twentynm_hssi_ver twentynm_hip_ver
altera lpm sgate altera_mf altera_lnsim twentynm twentynm_hssi twentynm_hip
quartus_qip_files = quartus_qip_files =
generated/ip_arria10_ddio_in_1.qip generated/ip_arria10_ddio_in_1.qip
generated/ip_arria10_ddio_out_1.qip generated/ip_arria10_ddio_out_1.qip
libraries/technology/ip_arria10/tse_sgmii_gx/hdllib.cfg
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− 4
View file @ 35cb7dd8
...@@ -13,9 +13,5 @@ synth_files = ...@@ -13,9 +13,5 @@ synth_files =
test_bench_files = test_bench_files =
tb_ip_arria10_tse_sgmii_gx.vhd tb_ip_arria10_tse_sgmii_gx.vhd
modelsim_search_libraries =
altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver twentynm_ver twentynm_hssi_ver twentynm_hip_ver
altera lpm sgate altera_mf altera_lnsim twentynm twentynm_hssi twentynm_hip
quartus_qip_files = quartus_qip_files =
generated/ip_arria10_tse_sgmii_gx.qip generated/ip_arria10_tse_sgmii_gx.qip
libraries/technology/ip_arria10/tse_sgmii_lvds/hdllib.cfg
+ 0
− 4
View file @ 35cb7dd8
...@@ -13,10 +13,6 @@ synth_files = ...@@ -13,10 +13,6 @@ synth_files =
test_bench_files = test_bench_files =
tb_ip_arria10_tse_sgmii_lvds.vhd tb_ip_arria10_tse_sgmii_lvds.vhd
modelsim_search_libraries =
altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver twentynm_ver twentynm_hssi_ver twentynm_hip_ver
altera lpm sgate altera_mf altera_lnsim twentynm twentynm_hssi twentynm_hip
quartus_qip_files = quartus_qip_files =
generated/ip_arria10_tse_sgmii_lvds.qip generated/ip_arria10_tse_sgmii_lvds.qip
libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/hdllib.cfg
+ 0
− 4
View file @ 35cb7dd8
...@@ -13,9 +13,5 @@ synth_files = ...@@ -13,9 +13,5 @@ synth_files =
test_bench_files = test_bench_files =
modelsim_search_libraries =
altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver stratixiv_ver stratixiv_hssi_ver stratixiv_pcie_hip_ver
altera lpm sgate altera_mf altera_lnsim stratixiv stratixiv_hssi stratixiv_pcie_hip
quartus_qip_files = quartus_qip_files =
generated/ip_stratixiv_ddr3_uphy_4g_800_master.qip generated/ip_stratixiv_ddr3_uphy_4g_800_master.qip
libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/hdllib.cfg
+ 0
− 4
View file @ 35cb7dd8
...@@ -12,9 +12,5 @@ synth_files = ...@@ -12,9 +12,5 @@ synth_files =
test_bench_files = test_bench_files =
modelsim_search_libraries =
altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver stratixiv_ver stratixiv_hssi_ver stratixiv_pcie_hip_ver
altera lpm sgate altera_mf altera_lnsim stratixiv stratixiv_hssi stratixiv_pcie_hip
quartus_qip_files = quartus_qip_files =
generated/ip_stratixiv_ddr3_uphy_4g_800_slave.qip generated/ip_stratixiv_ddr3_uphy_4g_800_slave.qip
libraries/technology/ip_stratixiv/mac_10g/hdllib.cfg
+ 0
− 4
View file @ 35cb7dd8
...@@ -13,10 +13,6 @@ synth_files = ...@@ -13,10 +13,6 @@ synth_files =
test_bench_files = test_bench_files =
modelsim_search_libraries =
altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver stratixiv_ver stratixiv_hssi_ver stratixiv_pcie_hip_ver
altera lpm sgate altera_mf altera_lnsim stratixiv stratixiv_hssi stratixiv_pcie_hip
modelsim_copy_files = modelsim_copy_files =
quartus_copy_files = quartus_copy_files =
......
libraries/technology/ip_stratixiv/phy_xaui/hdllib.cfg
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− 4
View file @ 35cb7dd8
...@@ -19,10 +19,6 @@ test_bench_files = ...@@ -19,10 +19,6 @@ test_bench_files =
tb_ip_stratixiv_phy_xaui.vhd tb_ip_stratixiv_phy_xaui.vhd
tb_ip_stratixiv_phy_xaui_ppm.vhd tb_ip_stratixiv_phy_xaui_ppm.vhd
modelsim_search_libraries =
altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver stratixiv_ver stratixiv_hssi_ver stratixiv_pcie_hip_ver
altera lpm sgate altera_mf altera_lnsim stratixiv stratixiv_hssi stratixiv_pcie_hip
modelsim_copy_files = modelsim_copy_files =
wave_tb_ip_stratixiv_phy_xaui.do . wave_tb_ip_stratixiv_phy_xaui.do .
wave_tb_ip_stratixiv_phy_xaui_ppm.do . wave_tb_ip_stratixiv_phy_xaui_ppm.do .
......
libraries/technology/mac_10g/hdllib.cfg
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View file @ 35cb7dd8
...@@ -23,10 +23,6 @@ test_bench_files = ...@@ -23,10 +23,6 @@ test_bench_files =
tb_tech_mac_10g.vhd tb_tech_mac_10g.vhd
tb_tb_tech_mac_10g.vhd tb_tb_tech_mac_10g.vhd
modelsim_search_libraries =
altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver twentynm_ver twentynm_hssi_ver twentynm_hip_ver
altera lpm sgate altera_mf altera_lnsim twentynm twentynm_hssi twentynm_hip
modelsim_copy_files = modelsim_copy_files =
wave_tb_tech_mac_10g_stratixiv.do . wave_tb_tech_mac_10g_stratixiv.do .
wave_tb_tech_mac_10g_arria10.do . wave_tb_tech_mac_10g_arria10.do .
libraries/technology/tse/hdllib.cfg
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− 3
View file @ 35cb7dd8
...@@ -20,6 +20,3 @@ test_bench_files = ...@@ -20,6 +20,3 @@ test_bench_files =
tb_tech_tse_pkg.vhd tb_tech_tse_pkg.vhd
tb_tech_tse.vhd tb_tech_tse.vhd
modelsim_search_libraries =
altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver twentynm_ver twentynm_hssi_ver twentynm_hip_ver
altera lpm sgate altera_mf altera_lnsim twentynm twentynm_hssi twentynm_hip
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