Change c_nof_channels constant into generic.

libraries/technology/10gbase_r/tb_tech_10gbase_r.vhd

@@ -48,7 +48,8 @@ USE tech_pll_lib.tech_pll_component_pkg.ALL;
 ENTITY tb_tech_10gbase_r IS
   -- Test bench control parameters
   GENERIC (
-    g_technology          : NATURAL := c_tech_select_default
+    g_technology          : NATURAL := c_tech_select_default;
+    g_nof_channels        : NATURAL := 24
   );
 END tb_tech_10gbase_r;
 
@@ -58,7 +59,6 @@ ARCHITECTURE tb OF tb_tech_10gbase_r IS
   CONSTANT c_sim               : BOOLEAN:= TRUE;
   CONSTANT c_sim_level         : NATURAL := 0;     -- 0 = use IP; 1 = use fast serdes model (not useful here, because no proper xgmii_tx_dc_arr stimuli)
   CONSTANT phy_loopback_delay  : TIME :=  sel_a_b(c_sim_level=0, 1 ns, 0 ns);
-  CONSTANT c_nof_channels      : NATURAL := 2;
   
   SIGNAL tb_end             : STD_LOGIC := '0';
   SIGNAL tr_ref_clk_644     : STD_LOGIC := '0';
@@ -66,17 +66,17 @@ ARCHITECTURE tb OF tb_tech_10gbase_r IS
   SIGNAL rst_156            : STD_LOGIC;
 
   -- XGMII interface
-  SIGNAL xgmii_tx_ready_arr : STD_LOGIC_VECTOR(c_nof_channels-1 DOWNTO 0);
-  SIGNAL xgmii_rx_ready_arr : STD_LOGIC_VECTOR(c_nof_channels-1 DOWNTO 0);
-  SIGNAL xgmii_tx_dc_arr    : t_xgmii_dc_arr(c_nof_channels-1 DOWNTO 0) := (OTHERS=>(OTHERS=>'0'));  -- '0', '1'
-  SIGNAL xgmii_rx_dc_arr    : t_xgmii_dc_arr(c_nof_channels-1 DOWNTO 0);
+  SIGNAL xgmii_tx_ready_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
+  SIGNAL xgmii_rx_ready_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
+  SIGNAL xgmii_tx_dc_arr    : t_xgmii_dc_arr(g_nof_channels-1 DOWNTO 0) := (OTHERS=>(OTHERS=>'0'));  -- '0', '1'
+  SIGNAL xgmii_rx_dc_arr    : t_xgmii_dc_arr(g_nof_channels-1 DOWNTO 0);
 
   -- PHY serial interface
   --SIGNAL link_fault         : STD_LOGIC := '1';   -- model initial link fault
   SIGNAL link_fault         : STD_LOGIC := '0';
-  SIGNAL tx_serial_arr      : STD_LOGIC_VECTOR(c_nof_channels-1 DOWNTO 0);
-  SIGNAL tx_serial_arr_dly  : STD_LOGIC_VECTOR(c_nof_channels-1 DOWNTO 0);
-  SIGNAL rx_serial_arr      : STD_LOGIC_VECTOR(c_nof_channels-1 DOWNTO 0);
+  SIGNAL tx_serial_arr      : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
+  SIGNAL tx_serial_arr_dly  : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
+  SIGNAL rx_serial_arr      : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
   
 BEGIN
 
@@ -110,10 +110,10 @@ BEGIN
 
   dut : ENTITY work.tech_10gbase_r
   GENERIC MAP (
-    g_technology       => g_technology,
-    g_sim              => c_sim,
-    g_sim_level        => c_sim_level,
-    g_nof_channels     => c_nof_channels
+    g_technology          => g_technology,
+    g_sim                 => c_sim,
+    g_sim_level           => c_sim_level,
+    g_nof_channels        => g_nof_channels
   )
   PORT MAP (
     -- Transceiver ATX PLL reference clock