Time tx_ready and rx_ready after tr_rst release. Otherwise tb_tb_tech_eth_10g...

Time tx_ready and rx_ready after tr_rst release. Otherwise tb_tb_tech_eth_10g u_sim misses the first packets.

libraries/technology/10gbase_r/sim_10gbase_r.vhd

@@ -93,7 +93,7 @@ BEGIN
     )
     PORT MAP(
       clk     => clk_156,
-      in_rst  => '0',
+      in_rst  => rst_156,
       out_rst => xgmii_tx_ready_arr(i)
     );
     
@@ -105,7 +105,7 @@ BEGIN
     )
     PORT MAP(
       clk     => clk_156,
-      in_rst  => '0',
+      in_rst  => rst_156,
       out_rst => xgmii_rx_ready_arr(i)
     );