Added c_use_sim_model for sim_10gbase_r.

libraries/technology/10gbase_r/tech_10gbase_r.vhd

@@ -31,6 +31,7 @@ ENTITY tech_10gbase_r IS
   GENERIC (
     g_technology     : NATURAL := c_tech_select_default;
     g_sim            : BOOLEAN := FALSE;
+    g_sim_level      : NATURAL := 0;     -- 0 = use IP; 1 = use fast serdes model
     g_nof_channels   : NATURAL := 1
   );
   PORT (
@@ -56,9 +57,12 @@ END tech_10gbase_r;
 
 ARCHITECTURE str OF tech_10gbase_r IS  
 
+  CONSTANT c_use_technology : BOOLEAN := g_sim = FALSE OR g_sim_level = 0;
+  CONSTANT c_use_sim_model  : BOOLEAN := NOT c_use_technology;
+  
 BEGIN
  
-  gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
+  gen_ip_arria10 : IF c_use_technology=TRUE AND g_technology=c_tech_arria10 GENERATE
     u0 : ENTITY work.tech_10gbase_r_arria10
     GENERIC MAP (g_sim, g_nof_channels)
     PORT MAP (tr_ref_clk_644,
@@ -67,5 +71,14 @@ BEGIN
               tx_serial_arr, rx_serial_arr);
   END GENERATE;
       
+  gem_sim_10gbase_r : IF c_use_sim_model=TRUE GENERATE
+    u0 : ENTITY work.sim_10gbase_r
+    GENERIC MAP (g_sim, g_nof_channels)
+    PORT MAP (tr_ref_clk_644,
+              clk_156, rst_156,
+              xgmii_tx_ready_arr, xgmii_rx_ready_arr, xgmii_tx_dc_arr, xgmii_rx_dc_arr,
+              tx_serial_arr, rx_serial_arr);
+  END GENERATE;
+  
 END str;