Added output tx_ready.

libraries/technology/10gbase_r/tb_tech_10gbase_r.vhd

@@ -51,17 +51,18 @@ ARCHITECTURE tb OF tb_tech_10gbase_r IS
   CONSTANT c_sim               : BOOLEAN:= TRUE;
   CONSTANT phy_loopback_delay  : TIME :=  1 ns;
   
-  SIGNAL tr_ref_clk_644    : STD_LOGIC := '0';
-  SIGNAL clk_156           : STD_LOGIC;
-  SIGNAL rst_156           : STD_LOGIC;
+  SIGNAL tr_ref_clk_644     : STD_LOGIC := '0';
+  SIGNAL clk_156            : STD_LOGIC;
+  SIGNAL rst_156            : STD_LOGIC;
 
   -- XGMII interface
-  SIGNAL xgmii_tx_dc_arr   : t_xgmii_dc_arr(g_nof_channels-1 DOWNTO 0);
-  SIGNAL xgmii_rx_dc_arr   : t_xgmii_dc_arr(g_nof_channels-1 DOWNTO 0);
+  SIGNAL xgmii_tx_ready_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
+  SIGNAL xgmii_tx_dc_arr    : t_xgmii_dc_arr(g_nof_channels-1 DOWNTO 0);
+  SIGNAL xgmii_rx_dc_arr    : t_xgmii_dc_arr(g_nof_channels-1 DOWNTO 0);
 
   -- PHY serial interface
-  SIGNAL tx_serial_arr     : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
-  SIGNAL rx_serial_arr     : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
+  SIGNAL tx_serial_arr      : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
+  SIGNAL rx_serial_arr      : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
   
 BEGIN
 
@@ -94,6 +95,7 @@ BEGIN
     rst_156            => rst_156,
 
     -- XGMII interface
+    xgmii_tx_ready_arr => xgmii_tx_ready_arr,
     xgmii_tx_dc_arr    => xgmii_tx_dc_arr,
     xgmii_rx_dc_arr    => xgmii_rx_dc_arr,
 

libraries/technology/10gbase_r/tech_10gbase_r.vhd

@@ -42,6 +42,7 @@ ENTITY tech_10gbase_r IS
     rst_156                 : IN STD_LOGIC;
 
     -- XGMII interface
+    xgmii_tx_ready_arr      : OUT STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
     xgmii_tx_dc_arr         : IN  t_xgmii_dc_arr(g_nof_channels-1 DOWNTO 0);  -- 72 bit
     xgmii_rx_dc_arr         : OUT t_xgmii_dc_arr(g_nof_channels-1 DOWNTO 0);  -- 72 bit
 
@@ -61,7 +62,7 @@ BEGIN
     GENERIC MAP (g_sim, g_nof_channels)
     PORT MAP (tr_ref_clk_644,
               clk_156, rst_156,
-              xgmii_tx_dc_arr, xgmii_rx_dc_arr,
+              xgmii_tx_ready_arr, xgmii_tx_dc_arr, xgmii_rx_dc_arr,
               tx_serial_arr, rx_serial_arr);
   END GENERATE;
       

libraries/technology/10gbase_r/tech_10gbase_r_arria10.vhd

@@ -46,6 +46,7 @@ ENTITY tech_10gbase_r_arria10 IS
     rst_156                 : IN STD_LOGIC;
 
     -- XGMII interface
+    xgmii_tx_ready_arr      : OUT STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
     xgmii_tx_dc_arr         : IN  t_xgmii_dc_arr(g_nof_channels-1 DOWNTO 0);  -- 72 bit
     xgmii_rx_dc_arr         : OUT t_xgmii_dc_arr(g_nof_channels-1 DOWNTO 0);  -- 72 bit
 
@@ -160,7 +161,7 @@ BEGIN
       pll_powerdown      => atx_pll_powerdown(I DOWNTO I),
       tx_analogreset     => tx_analogreset_arr(I DOWNTO I),
       tx_digitalreset    => tx_digitalreset_arr(I DOWNTO I),
-      tx_ready           => OPEN,
+      tx_ready           => xgmii_tx_ready_arr(I DOWNTO I),
       pll_locked         => atx_pll_locked_arr(I DOWNTO I),
       pll_select         => "0",                   -- set to zero when using one PLL
       tx_cal_busy        => cal_busy_arr(I DOWNTO I),