Added link_fault

libraries/technology/10gbase_r/tb_tech_10gbase_r.vhd

@@ -21,11 +21,19 @@
 
 -- Purpose: Testbench for tech_10gbase_r.
 -- Description:
---   The tb is not self checking.
---   The tb is used to investigate what clocks the 10gbase_r phy uses.
+-- . The tb is not self checking.
+-- . The tb is used to investigate what clocks the 10gbase_r phy uses.
+-- . The link fault is modelled on channel 0 only. Channel >= 1 is connected
+--   from the start and remains connected.
 -- Usage:
 --   > as 10
---   > run 100 us
+--   > run -a
+-- Observations:
+-- . With the link_fault it appears that tx_ready and rx_ready do not depend
+--   on whether the link is connected or not.
+--   A link fault does cause XGMII control to become 0x11 and data to become
+--   0x0100009C_0100009C. When the link is connected or reconnected then the
+--   XGMII control depends on xgmii_tx_dc_arr.
 
 LIBRARY IEEE, technology_lib, tech_pll_lib, common_lib;
 USE IEEE.std_logic_1164.ALL;
@@ -40,8 +48,7 @@ USE tech_pll_lib.tech_pll_component_pkg.ALL;
 ENTITY tb_tech_10gbase_r IS
   -- Test bench control parameters
   GENERIC (
-    g_technology    : NATURAL := c_tech_select_default;
-    g_nof_channels  : NATURAL := 4
+    g_technology          : NATURAL := c_tech_select_default
   );
 END tb_tech_10gbase_r;
 
@@ -50,24 +57,43 @@ ARCHITECTURE tb OF tb_tech_10gbase_r IS
 
   CONSTANT c_sim               : BOOLEAN:= TRUE;
   CONSTANT phy_loopback_delay  : TIME :=  1 ns;
+  CONSTANT c_nof_channels      : NATURAL := 2;
   
+  SIGNAL tb_end             : STD_LOGIC := '0';
   SIGNAL tr_ref_clk_644     : STD_LOGIC := '0';
   SIGNAL clk_156            : STD_LOGIC;
   SIGNAL rst_156            : STD_LOGIC;
 
   -- XGMII interface
-  SIGNAL xgmii_tx_ready_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
-  SIGNAL xgmii_tx_dc_arr    : t_xgmii_dc_arr(g_nof_channels-1 DOWNTO 0);
-  SIGNAL xgmii_rx_dc_arr    : t_xgmii_dc_arr(g_nof_channels-1 DOWNTO 0);
+  SIGNAL xgmii_tx_ready_arr : STD_LOGIC_VECTOR(c_nof_channels-1 DOWNTO 0);
+  SIGNAL xgmii_rx_ready_arr : STD_LOGIC_VECTOR(c_nof_channels-1 DOWNTO 0);
+  SIGNAL xgmii_tx_dc_arr    : t_xgmii_dc_arr(c_nof_channels-1 DOWNTO 0) := (OTHERS=>(OTHERS=>'X'));  -- '0', '1'
+  SIGNAL xgmii_rx_dc_arr    : t_xgmii_dc_arr(c_nof_channels-1 DOWNTO 0);
 
   -- PHY serial interface
-  SIGNAL tx_serial_arr      : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
-  SIGNAL rx_serial_arr      : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
+  --SIGNAL link_fault         : STD_LOGIC := '1';   -- model initial link fault
+  SIGNAL link_fault         : STD_LOGIC := '0';
+  SIGNAL tx_serial_arr      : STD_LOGIC_VECTOR(c_nof_channels-1 DOWNTO 0);
+  SIGNAL tx_serial_arr_dly  : STD_LOGIC_VECTOR(c_nof_channels-1 DOWNTO 0);
+  SIGNAL rx_serial_arr      : STD_LOGIC_VECTOR(c_nof_channels-1 DOWNTO 0);
   
 BEGIN
 
   tr_ref_clk_644 <= NOT tr_ref_clk_644 AFTER tech_pll_clk_644_period/2;
 
+  p_stimuli : PROCESS
+  BEGIN
+    WAIT FOR 50 us;
+    -- Model a link fault to verify Rx recovery
+    link_fault <= '1';
+    WAIT FOR 10 us;
+    link_fault <= '0';
+    WAIT FOR 10 us;
+    tb_end <= '1';
+    REPORT "Tb simulation finished." SEVERITY FAILURE;
+    WAIT;
+  END PROCESS;
+
   pll : ENTITY tech_pll_lib.tech_pll_xgmii_mac_clocks
   GENERIC MAP (
     g_technology => g_technology
@@ -84,7 +110,7 @@ BEGIN
   GENERIC MAP (
     g_technology       => g_technology,
     g_sim              => c_sim,
-    g_nof_channels     => g_nof_channels
+    g_nof_channels     => c_nof_channels
   )
   PORT MAP (
     -- Transceiver ATX PLL reference clock
@@ -96,6 +122,7 @@ BEGIN
 
     -- XGMII interface
     xgmii_tx_ready_arr => xgmii_tx_ready_arr,
+    xgmii_rx_ready_arr => xgmii_rx_ready_arr,
     xgmii_tx_dc_arr    => xgmii_tx_dc_arr,
     xgmii_rx_dc_arr    => xgmii_rx_dc_arr,
 
@@ -105,6 +132,14 @@ BEGIN
   );
   
   -- PHY loopback
-  rx_serial_arr <= TRANSPORT tx_serial_arr AFTER phy_loopback_delay;
+  tx_serial_arr_dly <= TRANSPORT tx_serial_arr AFTER phy_loopback_delay;
+  
+  p_link : PROCESS(tx_serial_arr_dly, link_fault)
+  BEGIN
+    rx_serial_arr <= tx_serial_arr_dly;
+    IF link_fault='1' THEN
+      rx_serial_arr(0) <= '0';  -- model link fault only for channel 0
+    END IF;
+  END PROCESS;
   
 END tb;