Created the new unb2c_test_ddr_16G_I revision.

This reverts commit ef19a04f, reversing
changes made to 4a55fb28.

Removed dvr_clk, because it is the mm_clk. Fixed use g_cross_domain_dvr_ctlr = TRUE to get between mm_clk and ctlr_clk_in.

Removed clock domain crossing logic for this control register, because that is done by io_ddr_cross_domain.vhd in io_ddr.vhd. Removed cal_fail and cal_ok, because these are already available via the io_ddr status register.

Added draft src/vhdl/mms_io_ddr_diag.vhd, it intstantiates the BG, DB and IO_DDR as is and it compiles.

Corrected asserting ctlr_mosi.burstbegin for only one clock cycle as specified in the uniphy emi_ip.pdf manual.

-Enabled this model in tb_apertif_unb1_fn_beamformer_tp_bg.

- Switched fail and ok in reg map
- Removed comments  

Removed internal DDR memory model (now needs to be instantiated in tb). Use dedicated records for DDR3 and DDR4 phy interfaces, instead of the combined record.