removed latch from io_ddr_reg

libraries/io/ddr/src/vhdl/io_ddr_reg.vhd

@@ -78,7 +78,7 @@ architecture rtl of io_ddr_reg is
                                          nof_dat  => 8,
                                          init_sl  => '0');
 
-  signal i_dvr_mosi        : t_mem_ctlr_mosi;
+  signal i_dvr_mosi        : t_mem_ctlr_mosi := c_mem_ctlr_mosi_rst;
 begin
   dvr_mosi <= i_dvr_mosi;
 
@@ -102,6 +102,8 @@ begin
 
       -- Write access defaults
       i_dvr_mosi.burstbegin <= '0';
+      i_dvr_mosi.wrdata <= (others => '0'); -- no data is set, only control signals.
+      i_dvr_mosi.rd <= '0'; -- = no need to control i_dvr_mosi.rd as i_dvr_mosi.wr = wr_not_rd.
 
       -- Write access: set register value
       if sla_in.wr = '1' then