Commits · 936dba67ff3d9103b82f9c5dec527024f3ec90c4 · RTSD / HDL · GitLab

Snippets Groups Projects

May 15, 2023
- Add comment about sim_ddr size. · 936dba67
  Eric Kooistra authored 1 year ago
  
  936dba67
May 11, 2023
- Define ddr_gigabytes as integer to be able to represent both > 1GB (HW) and < 1GB (sim) sizes. · aac5f892
  Eric Kooistra authored 1 year ago
  
  aac5f892
Mar 21, 2023
- Add and verify ctlr_nof_bytes_per_word field in reg_io_ddr. · c37576fd
  Eric Kooistra authored 2 years ago
  
  c37576fd
- Add and verify ddr_gigabytes field in reg_io_ddr. · 71e29da7
  Eric Kooistra authored 2 years ago
  
  71e29da7
Mar 20, 2023
- Add c_tech_ddr4_16g_1600m_64, c_tech_ddr4_16g_1600m_72_64 options. · 590e7fd3
  Eric Kooistra authored 2 years ago
  
  590e7fd3
- Add missing hex files for 16G 64b and 72b. · 379160e7
  Eric Kooistra authored 2 years ago
  
  379160e7
Dec 21, 2022
- L2SDP-880 , backup changes · aef102a0
  Pieter Donker authored 2 years ago
  
  aef102a0
Jun 07, 2022
- Remove TO_UINT for vectors wider than 32 bits. · 5de47ef0
  Job van Wee authored 2 years ago
  
  5de47ef0
Jun 03, 2022
- Making a hardware test. · 70d3f14e
  Job van Wee authored 2 years ago
  
  70d3f14e
Jan 19, 2022
- Fix simulating DDR4 for unb2c, except for fverifying the dbg_rd_data. · 5174b894
  Eric Kooistra authored 3 years ago
  
  5174b894
- Work around for verifying DDR4 on unb2c. · ae27c70e
  Eric Kooistra authored 3 years ago
  
  ae27c70e
- Added copy_hex_files.tcl for Unb2b and Unb2c 8GB DDR4 driver. · 935510bc
  Eric Kooistra authored 3 years ago
  
  935510bc
Oct 13, 2021
- processed review comments · 64411310
  Reinier van der Walle authored 3 years ago
  
  64411310
- added yaml entries for unb2c_test design · e9c44d8c
  Reinier van der Walle authored 3 years ago
  
  e9c44d8c
Aug 22, 2019
- backup last changes, build for unb2b not working · b0c776a4
  Pieter Donker authored 5 years ago
  
  b0c776a4
Jul 31, 2018
- fixed the FIXME in io_ddr testbench · f9e6bc4b
  Reinier van der Walle authored 6 years ago
  
  f9e6bc4b
Jul 30, 2018
- placed u_sim_model under gen_ddr3 such that it will not be used for DDR4... · d2c123fa
  Reinier van der Walle authored 6 years ago
  d2c123fa
- added copy_hex_files.tcl for ip_arria10_e1sg · d52a9e8c
  Reinier van der Walle authored 6 years ago
  
  d52a9e8c
Dec 08, 2017
- Imporved g_sim_model description comment. · c8ebfe11
  Eric Kooistra authored 7 years ago
  
  c8ebfe11
Jun 13, 2017
- Fixed DDR simulation model. · a2f529f6
  Eric Kooistra authored 7 years ago
  
  a2f529f6
Mar 17, 2017
- Added proc_common_timeout_failure(). · d52574e6
  Eric Kooistra authored 8 years ago
  
  d52574e6
Oct 31, 2016
- Added extra register for rd_fifo_full bit and wr_fifo_full bit. · 7fb08f74
  Pepping authored 8 years ago
  
  7fb08f74
May 11, 2016
- Added regression_test_vhdl with tb. · 6faf1e4a
  Eric Kooistra authored 8 years ago
  
  6faf1e4a
- Use tb_end signal. · 5787dd18
  Eric Kooistra authored 8 years ago
  
  5787dd18
Apr 28, 2016
- Removed tech_ddr3 because it is unknown. · 506d8cea
  Eric Kooistra authored 8 years ago
  
  506d8cea
Apr 19, 2016
- Added [section headers]. · b232c8c7
  Eric Kooistra authored 9 years ago
  
  b232c8c7
Oct 18, 2015
- Added and pass on g_technology. · 9c281f47
  Eric Kooistra authored 9 years ago
  
  9c281f47
Jul 09, 2015
- Pass on ctlr_miso.done to wr_snk_out.xon to support XON flow control. · d48977ca
  Eric Kooistra authored 9 years ago
  
  d48977ca
Jun 30, 2015
- Removed clock period generics. Corrected c_ctlr_ref_clk_period = 25 MHz for DDR4. · 43931c4b
  Eric Kooistra authored 9 years ago
  
  43931c4b
Jun 26, 2015
- Use separate g_dp_wr_fifo_depth and g_dp_rd_fifo_depth. · fbadd894
  Eric Kooistra authored 9 years ago
  
  fbadd894
- Derive g_rd_fifo_af_margin internally in io_ddr.vhd based on g_tech_ddr.name=DDR3 or DDR4. · 12fd53ea
  Eric Kooistra authored 9 years ago
  
  12fd53ea
Jun 25, 2015
- Removed dvr_clk, because it is the mm_clk. Fixed use g_cross_domain_dvr_ctlr =... · 755f1acb
  Eric Kooistra authored 9 years ago
  755f1acb
- Used g_cross_domain_delay_len=c_meta_delay_len fixed instead of via generic. · a8775752
  Eric Kooistra authored 9 years ago
  
  a8775752
- Removed clock domain crossing logic for this control register, because that is... · edb2c90e
  Eric Kooistra authored 9 years ago
  edb2c90e
- Used g_cross_domain_delay_len=c_meta_delay_len fixed instead of via generic. · 298065ab
  Eric Kooistra authored 9 years ago
  
  298065ab
Jun 24, 2015
- Register ctlr_wr_flush_en to ease timing closure. · df1c1e28
  Eric Kooistra authored 9 years ago
  
  df1c1e28
Jun 12, 2015
- Added g_sim_model. · 33e83b5a
  Eric Kooistra authored 9 years ago
  
  33e83b5a
- Added g_sim_model. Renamed instances. · 0306fe4b
  Eric Kooistra authored 9 years ago
  
  0306fe4b
- Provide streaming access to IO_DDR using a Tx seq and a Rx seq with optional DB RAM. · 61f16974
  Eric Kooistra authored 9 years ago
  
  61f16974
Jun 11, 2015
- Added draft src/vhdl/mms_io_ddr_diag.vhd, it intstantiates the BG, DB and... · 4e1d928d
  Eric Kooistra authored 9 years ago
  4e1d928d