Instantiate tech_ddr_lib.tech_ddr_memory_model. Use dp_clk for rd and wr. DDR3 access starts but diagnostic result fails.diff

Defined c_tech_ddr_max_ctrl_data_w and c_tech_ddr_max_ctrl_address_w. Added odt_w field. Moved clk from t_tech_ddr_phy_in to t_tech_ddr_phy_out. Renamed record fields.

Compile DDR3 memory model from the ip_stratixiv_ddr3_uphy_4g_800_master example design into this library.

Added '+nowarnTFMPC +nowarnPCDPC' to simulation configurationto have nowarn on verilog IP connection mismatch warnings.

-Added wpfb_unit to apertif_unb1_correlator.vhd;
-Removed FIFOs and dp_src_out_timers from apertif_unb1_correlator.vhd.

Added functions func_tech_ddr_dq_address_w() and func_tech_ddr_data_address_w(). Added field name and cs_w_w to t_c_tech_ddr record type.

 . dsp/fft
 . dsp/filter
 . dsp/frTwoSDF
 . dsp/wpfb
 . Lofar/st
 This allows synthesis of design apertif_unb1_correlator.

Ported $UNB ddr3_flush_ctrl.vhd to $RADIOHDL io_ddr_driver_flush_ctrl.vhd. Initial version, still needs to be compiled and simulated with tb_io_ddr.vhd.

Ported $UNB ddr3.vhd to $RADIOHDL io_ddr.vhd. Initial version, still needs to be compiled and simulated with tb_io_ddr.vhd.

-Modified gen_hex_files_complex_subbands to generate folded data.
=>Now the correlator accepts interleaved inputs as well.