Added functions func_tech_ddr_dq_address_w() and...

Added functions func_tech_ddr_dq_address_w() and func_tech_ddr_data_address_w(). Added field name and cs_w_w to t_c_tech_ddr record type.

libraries/technology/ddr/tech_ddr_pkg.vhd

@@ -29,6 +29,7 @@ PACKAGE tech_ddr_pkg IS
   -- Gather all parameters in one record
   TYPE t_c_tech_ddr IS RECORD
     -- PHY variant within a technology
+    name                              : STRING(1 TO 4);  -- = "DDR3" or "DDR4"
     mts                               : NATURAL;  -- = 800   access rate in mega transfers per second
     master                            : BOOLEAN;  -- = TRUE  TRUE = uniphy master, FALSE = uniphy slave regarding OCT and terminationcontrol for DDR3
     -- PHY external FPGA IO
@@ -39,7 +40,8 @@ PACKAGE tech_ddr_pkg IS
     dq_w                              : NATURAL;  -- = 64
     dqs_w                             : NATURAL;  -- = 8      = dq_w / nof_dq_per_dqs
     dm_w                              : NATURAL;  -- = 8
-    cs_w                              : NATURAL;  -- = 2
+    cs_w                              : NATURAL;  -- = 2      = number of chip select lines
+    cs_w_w                            : NATURAL;  -- = 1      = true_log2(cs_w), use when the number of chip select lines is converted to a logical address
     clk_w                             : NATURAL;  -- = 2
     -- PHY internal FPGA IO
     terminationcontrol_w              : NATURAL;  -- = 14     internal bus in FPGA
@@ -52,11 +54,14 @@ PACKAGE tech_ddr_pkg IS
     maxburstsize_w                    : NATURAL;  -- = 7      = ceil_log2(maxburstsize+1)
   END RECORD;
   
-  CONSTANT c_tech_ddr_max             : t_c_tech_ddr := ( 800,  TRUE,   16, 16, 10, 3, 64, 8, 8, 2, 2,   14,   4, 2, 32, 256, 64, 7);  -- maximum ranges for record field definitions
-  CONSTANT c_tech_ddr_4g_800m         : t_c_tech_ddr := ( 800,  TRUE,   15, 15, 10, 3, 64, 8, 8, 2, 2,   14,   4, 2, 32, 256, 64, 7);
-  CONSTANT c_tech_ddr_4g_800m_slave   : t_c_tech_ddr := ( 800, FALSE,   15, 15, 10, 3, 64, 8, 8, 2, 2,   14,   4, 2, 32, 256, 64, 7);
+  CONSTANT c_tech_ddr_max             : t_c_tech_ddr := ("none", 800,  TRUE,   16, 16, 10, 3, 64, 8, 8, 2, 1, 2,   14,   4, 2, 32, 256, 64, 7);  -- maximum ranges for record field definitions
+  CONSTANT c_tech_ddr_4g_800m         : t_c_tech_ddr := ("none", 800,  TRUE,   15, 15, 10, 3, 64, 8, 8, 2, 1, 2,   14,   4, 2, 32, 256, 64, 7);
+  CONSTANT c_tech_ddr3_4g_800m_master : t_c_tech_ddr := ("DDR3", 800, FALSE,   15, 15, 10, 3, 64, 8, 8, 2, 1, 2,   14,   4, 2, 32, 256, 64, 7);
+  CONSTANT c_tech_ddr3_4g_800m_slave  : t_c_tech_ddr := ("DDR3", 800, FALSE,   15, 15, 10, 3, 64, 8, 8, 2, 1, 2,   14,   4, 2, 32, 256, 64, 7);
 
-  FUNCTION func_tech_ddr_module_size(c_ddr : t_c_tech_ddr) RETURN NATURAL;  -- return DDR module size in GByte
+  FUNCTION func_tech_ddr_dq_address_w(  c_ddr : t_c_tech_ddr) RETURN NATURAL;  -- return DDR address width for the DQ data at the PHY mts rate
+  FUNCTION func_tech_ddr_data_address_w(c_ddr : t_c_tech_ddr) RETURN NATURAL;  -- return DDR address width for the controller data at the by rsl=4 reduced rate
+  FUNCTION func_tech_ddr_module_size(   c_ddr : t_c_tech_ddr) RETURN NATURAL;  -- return DDR module size in GByte
     
   -- PHY in, inout and out signal records
   TYPE t_tech_ddr_phy_in IS RECORD  
@@ -102,17 +107,14 @@ PACKAGE tech_ddr_pkg IS
 
   -- PHY address signal record
   TYPE t_tech_ddr_addr IS RECORD 
-    chip      : STD_LOGIC_VECTOR(ceil_log2(c_tech_ddr_max.cs_w)  -1 DOWNTO 0);  -- Use ceil_log2() because the controller interprets the chip address as logical address (NOT individual chip select lines)
-    bank      : STD_LOGIC_VECTOR(          c_tech_ddr_max.ba_w   -1 DOWNTO 0);
-    row       : STD_LOGIC_VECTOR(          c_tech_ddr_max.a_row_w-1 DOWNTO 0); 
-    column    : STD_LOGIC_VECTOR(          c_tech_ddr_max.a_col_w-1 DOWNTO 0);
+    chip      : STD_LOGIC_VECTOR(c_tech_ddr_max.cs_w_w)-1 DOWNTO 0);
+    bank      : STD_LOGIC_VECTOR(c_tech_ddr_max.ba_w   -1 DOWNTO 0);
+    row       : STD_LOGIC_VECTOR(c_tech_ddr_max.a_row_w-1 DOWNTO 0); 
+    column    : STD_LOGIC_VECTOR(c_tech_ddr_max.a_col_w-1 DOWNTO 0);
   END RECORD;
 
   TYPE t_tech_ddr_addr_arr IS ARRAY(NATURAL RANGE <>) OF t_tech_ddr_addr; 
   
-  CONSTANT c_tech_ddr_ctrl_nof_latent_reads : NATURAL := 100;  -- Due to having a command cue, even after de-asserting read requests, the PHY keeps processing the cued read requests. 
-                                                               -- This makes sure 100 words are still available in the read FIFO after it de-asserted its siso.ready signal towards the ddr3 read side.
-                                                          
   CONSTANT c_tech_ddr_addr_lo          : t_tech_ddr_addr := ((OTHERS=>'0'), (OTHERS=>'0'), (OTHERS=>'0'), (OTHERS=>'0'));
   CONSTANT c_tech_ddr_addr_hi_4gb_800m : t_tech_ddr_addr := ((OTHERS=>'1'), (OTHERS=>'1'), (OTHERS=>'1'), TO_UVEC(2**c_tech_ddr_4g_800m.a_col_w - c_tech_ddr_4g_800m.rsl, c_tech_ddr_4g_800m.a_col_w));
   CONSTANT c_tech_ddr_addr_hi_sim      : t_tech_ddr_addr := ((OTHERS=>'0'), (OTHERS=>'0'), TO_UVEC(3, c_tech_ddr_4g_800m.a_row_w),  TO_UVEC(2**c_tech_ddr_4g_800m.a_col_w - c_tech_ddr_4g_800m.rsl, c_tech_ddr_4g_800m.a_col_w));
@@ -137,9 +139,19 @@ END tech_ddr_pkg;
 
 PACKAGE BODY tech_ddr_pkg IS
 
+  FUNCTION func_tech_ddr_dq_address_w(c_ddr : t_c_tech_ddr) RETURN NATURAL IS
+  BEGIN
+    RETURN c_ddr.cs_w_w + c_ddr.ba_w + c_ddr.a_w + c_ddr.a_col_w;
+  END;
+  
+  FUNCTION func_tech_ddr_data_address_w(c_ddr : t_c_tech_ddr) RETURN NATURAL IS
+    CONSTANT c_dq_address_w : NATURAL := func_tech_ddr_dq_address_w(c_ddr);
+  BEGIN
+    RETURN c_dq_address_w-c_ddr.rsl_w;
+  END;
+  
   FUNCTION func_tech_ddr_module_size(c_ddr : t_c_tech_ddr) RETURN NATURAL IS
-    CONSTANT c_chip_addr_w        : NATURAL := ceil_log2(c_ddr.cs_w);  -- Chip sel lines converted to logical address
-    CONSTANT c_dq_address_w       : NATURAL := c_chip_addr_w + c_ddr.ba_w + c_ddr.a_w + c_ddr.a_col_w;
+    CONSTANT c_dq_address_w       : NATURAL := func_tech_ddr_dq_address_w(c_ddr);
     CONSTANT c_dq_nof_bytes_w     : NATURAL := 8;  -- both dw_q = 64 and 72 are regarded as having 8 bytes (either with 8 or 9 bits per byte)
     CONSTANT c_module_nof_bytes_w : NATURAL := c_dq_address_w + c_dq_nof_bytes_w;
     CONSTANT c_1GB_w              : NATURAL := 30;
@@ -147,5 +159,6 @@ PACKAGE BODY tech_ddr_pkg IS
     RETURN 2**(c_module_nof_bytes_w-c_1GB_w);
   END;
   
+  
 END tech_ddr_pkg;