Skip to content

GitLab

Explore

Sign in

Primary navigation

Project

H

HDL
- Activity
- Members
- Labels
- Issues
- Issue boards
- Milestones
- Iterations
- Wiki
- Requirements
- Jira
- Environments
- Incidents

Snippets Groups Projects

de6d154f

Commit de6d154f authored 10 years ago by Eric Kooistra

Downloads
- Patches
- Plain Diff

Compile DDR3 memory model from the ip_stratixiv_ddr3_uphy_4g_800_master...

Compile DDR3 memory model from the ip_stratixiv_ddr3_uphy_4g_800_master example design into this library.

parent cfe1fbd0

No related branches found

No related tags found

Loading

Changes 3

Hide whitespace changes

Inline Side-by-side

Showing

libraries/technology/ip_stratixiv/ddr3_mem_model/compile_ip.tcl 36 additions, 0 deletions

...ies/technology/ip_stratixiv/ddr3_mem_model/compile_ip.tcl
libraries/technology/ip_stratixiv/ddr3_mem_model/generate_ip.sh 48 additions, 0 deletions

...ies/technology/ip_stratixiv/ddr3_mem_model/generate_ip.sh
libraries/technology/ip_stratixiv/ddr3_mem_model/hdllib.cfg 14 additions, 0 deletions

libraries/technology/ip_stratixiv/ddr3_mem_model/hdllib.cfg

with 98 additions and 0 deletions

Loading

0% Loading or .

You are about to add 0 people to the discussion. Proceed with caution.

Finish editing this message first!

Please register or sign in to comment