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Commit 3c8fc0e5 authored by Eric Kooistra's avatar Eric Kooistra
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Gather all DDR parameters in one t_c_tech_ddr record

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libraries/technology/ddr/tech_ddr_pkg.vhd
+ 59
− 54
View file @ 3c8fc0e5
...@@ -26,54 +26,68 @@ USE common_lib.common_pkg.ALL; ...@@ -26,54 +26,68 @@ USE common_lib.common_pkg.ALL;
PACKAGE tech_ddr_pkg IS PACKAGE tech_ddr_pkg IS
-- DDR3 -- Gather all parameters in one record
TYPE t_c_tech_ddr_phy IS RECORD TYPE t_c_tech_ddr IS RECORD
a_w : NATURAL; -- = 16; -- PHY variant within a technology
a_row_w : NATURAL; -- = 16; -- = a_w, row address width, via a_w lines mts : NATURAL; -- = 800 access rate in mega transfers per second
a_col_w : NATURAL; -- = 10; -- <= a_w, col address width, via a_w lines master : BOOLEAN; -- = TRUE TRUE = uniphy master, FALSE = uniphy slave regarding OCT and terminationcontrol for DDR3
ba_w : NATURAL; -- = 3; -- PHY external FPGA IO
dq_w : NATURAL; -- = 64; a_w : NATURAL; -- = 16
dqs_w : NATURAL; -- = 8; -- = dq_w / nof_dq_per_dqs; a_row_w : NATURAL; -- = 16 = a_w, row address width, via a_w lines
dm_w : NATURAL; -- = 8; a_col_w : NATURAL; -- = 10 <= a_w, col address width, via a_w lines
cs_w : NATURAL; -- = 2; ba_w : NATURAL; -- = 3
clk_w : NATURAL; -- = 2; dq_w : NATURAL; -- = 64
terminationcontrol_w : NATURAL; -- = 14; dqs_w : NATURAL; -- = 8 = dq_w / nof_dq_per_dqs;
dm_w : NATURAL; -- = 8
cs_w : NATURAL; -- = 2
clk_w : NATURAL; -- = 2
-- PHY internal FPGA IO
terminationcontrol_w : NATURAL; -- = 14 internal bus in FPGA
-- Controller
rsl : NATURAL; -- = 4 = 2 (use both PHY clock edges) * 2 (PHY transfer at double rate), resolution
rsl_w : NATURAL; -- = 2 = ceil_log2(rsl)
address_w : NATURAL; -- = 32 = (2**32)*c_tech_ddr_phy.dq_w/c_byte_w bytes
data_w : NATURAL; -- = 256 = rsl * c_tech_ddr_phy.dq_w
maxburstsize : NATURAL; -- = 64
maxburstsize_w : NATURAL; -- = 7 = ceil_log2(maxburstsize+1)
END RECORD; END RECORD;
CONSTANT c_tech_ddr_phy : t_c_tech_ddr_phy := (16, 16, 10, 3, 64, 8, 8, 2, 2, 14); CONSTANT c_tech_ddr_max : t_c_tech_ddr := ( 800, TRUE, 16, 16, 10, 3, 64, 8, 8, 2, 2, 14, 4, 2, 32, 256, 64, 7); -- maximum ranges for record field definitions
CONSTANT c_tech_ddr_phy_4g : t_c_tech_ddr_phy := (15, 15, 10, 3, 64, 8, 8, 2, 2, 14); CONSTANT c_tech_ddr_4g_800m : t_c_tech_ddr := ( 800, TRUE, 15, 15, 10, 3, 64, 8, 8, 2, 2, 14, 4, 2, 32, 256, 64, 7);
CONSTANT c_tech_ddr_4g_800m_slave : t_c_tech_ddr := ( 800, FALSE, 15, 15, 10, 3, 64, 8, 8, 2, 2, 14, 4, 2, 32, 256, 64, 7);
-- PHY in, inout and out signal records
TYPE t_tech_ddr_phy_in IS RECORD TYPE t_tech_ddr_phy_in IS RECORD
evt : STD_LOGIC; -- event signal is Not Connected to DDR3 PHY evt : STD_LOGIC; -- event signal is Not Connected to DDR3 PHY
oct_rup : STD_LOGIC; -- only master DDR3 PHY has On Chip Termination OCT inputs oct_rup : STD_LOGIC; -- only master DDR3 PHY has On Chip Termination OCT inputs
oct_rdn : STD_LOGIC; -- only master DDR3 PHY has On Chip Termination OCT inputs oct_rdn : STD_LOGIC; -- only master DDR3 PHY has On Chip Termination OCT inputs
seriesterminationcontrol : STD_LOGIC_VECTOR(c_tech_ddr_phy.terminationcontrol_w-1 DOWNTO 0); -- termination control to slave from master DDR3 PHY seriesterminationcontrol : STD_LOGIC_VECTOR(c_tech_ddr_max.terminationcontrol_w-1 DOWNTO 0); -- termination control to slave from master DDR3 PHY (internal signal in FPGA)
parallelterminationcontrol : STD_LOGIC_VECTOR(c_tech_ddr_phy.terminationcontrol_w-1 DOWNTO 0); -- termination control to slave from master DDR3 PHY parallelterminationcontrol : STD_LOGIC_VECTOR(c_tech_ddr_max.terminationcontrol_w-1 DOWNTO 0); -- termination control to slave from master DDR3 PHY (internal signal in FPGA)
END RECORD; END RECORD;
TYPE t_tech_ddr_phy_io IS RECORD TYPE t_tech_ddr_phy_io IS RECORD
dq : STD_LOGIC_VECTOR(c_tech_ddr_phy.dq_w-1 DOWNTO 0); -- data bus dq : STD_LOGIC_VECTOR(c_tech_ddr_max.dq_w-1 DOWNTO 0); -- data bus
dqs : STD_LOGIC_VECTOR(c_tech_ddr_phy.dqs_w-1 DOWNTO 0); -- data strobe bus dqs : STD_LOGIC_VECTOR(c_tech_ddr_max.dqs_w-1 DOWNTO 0); -- data strobe bus
dqs_n : STD_LOGIC_VECTOR(c_tech_ddr_phy.dqs_w-1 DOWNTO 0); dqs_n : STD_LOGIC_VECTOR(c_tech_ddr_max.dqs_w-1 DOWNTO 0);
clk : STD_LOGIC_VECTOR(c_tech_ddr_phy.clk_w-1 DOWNTO 0); -- clock, positive edge clock clk : STD_LOGIC_VECTOR(c_tech_ddr_max.clk_w-1 DOWNTO 0); -- clock, positive edge clock
clk_n : STD_LOGIC_VECTOR(c_tech_ddr_phy.clk_w-1 DOWNTO 0); -- clock, negative edge clock clk_n : STD_LOGIC_VECTOR(c_tech_ddr_max.clk_w-1 DOWNTO 0); -- clock, negative edge clock
scl : STD_LOGIC; -- I2C scl : STD_LOGIC; -- I2C
sda : STD_LOGIC; sda : STD_LOGIC;
END RECORD; END RECORD;
TYPE t_tech_ddr_phy_ou IS RECORD TYPE t_tech_ddr_phy_ou IS RECORD
a : STD_LOGIC_VECTOR(c_tech_ddr_phy.a_w-1 DOWNTO 0); -- row and column address a : STD_LOGIC_VECTOR(c_tech_ddr_max.a_w-1 DOWNTO 0); -- row and column address
ba : STD_LOGIC_VECTOR(c_tech_ddr_phy.ba_w-1 DOWNTO 0); -- bank address ba : STD_LOGIC_VECTOR(c_tech_ddr_max.ba_w-1 DOWNTO 0); -- bank address
dm : STD_LOGIC_VECTOR(c_tech_ddr_phy.dm_w-1 DOWNTO 0); -- data mask bus dm : STD_LOGIC_VECTOR(c_tech_ddr_max.dm_w-1 DOWNTO 0); -- data mask bus
cas_n : STD_LOGIC; -- column address strobe cas_n : STD_LOGIC; -- column address strobe
ras_n : STD_LOGIC; -- row address strobe ras_n : STD_LOGIC; -- row address strobe
we_n : STD_LOGIC; -- write enable signal we_n : STD_LOGIC; -- write enable signal
reset_n : STD_LOGIC; -- reset signal reset_n : STD_LOGIC; -- reset signal
odt : STD_LOGIC_VECTOR(c_tech_ddr_phy.cs_w-1 DOWNTO 0); -- on-die termination control signal odt : STD_LOGIC_VECTOR(c_tech_ddr_max.cs_w-1 DOWNTO 0); -- on-die termination control signal
cke : STD_LOGIC_VECTOR(c_tech_ddr_phy.cs_w-1 DOWNTO 0); -- clock enable cke : STD_LOGIC_VECTOR(c_tech_ddr_max.cs_w-1 DOWNTO 0); -- clock enable
cs_n : STD_LOGIC_VECTOR(c_tech_ddr_phy.cs_w-1 DOWNTO 0); -- chip select cs_n : STD_LOGIC_VECTOR(c_tech_ddr_max.cs_w-1 DOWNTO 0); -- chip select
seriesterminationcontrol : STD_LOGIC_VECTOR(c_tech_ddr_phy.terminationcontrol_w-1 DOWNTO 0); -- termination control from master to slave DDR3 PHY seriesterminationcontrol : STD_LOGIC_VECTOR(c_tech_ddr_max.terminationcontrol_w-1 DOWNTO 0); -- termination control from master to slave DDR3 PHY (internal signal in FPGA)
parallelterminationcontrol : STD_LOGIC_VECTOR(c_tech_ddr_phy.terminationcontrol_w-1 DOWNTO 0); -- termination control from master to slave DDR3 PHY parallelterminationcontrol : STD_LOGIC_VECTOR(c_tech_ddr_max.terminationcontrol_w-1 DOWNTO 0); -- termination control from master to slave DDR3 PHY (internal signal in FPGA)
END RECORD; END RECORD;
CONSTANT c_tech_ddr_phy_in_rst : t_tech_ddr_phy_in := ('0', 'X', 'X', (OTHERS=>'X'), (OTHERS=>'X')); CONSTANT c_tech_ddr_phy_in_rst : t_tech_ddr_phy_in := ('0', 'X', 'X', (OTHERS=>'X'), (OTHERS=>'X'));
...@@ -84,46 +98,37 @@ PACKAGE tech_ddr_pkg IS ...@@ -84,46 +98,37 @@ PACKAGE tech_ddr_pkg IS
TYPE t_tech_ddr_phy_io_arr IS ARRAY(NATURAL RANGE <>) OF t_tech_ddr_phy_io; TYPE t_tech_ddr_phy_io_arr IS ARRAY(NATURAL RANGE <>) OF t_tech_ddr_phy_io;
TYPE t_tech_ddr_phy_ou_arr IS ARRAY(NATURAL RANGE <>) OF t_tech_ddr_phy_ou; TYPE t_tech_ddr_phy_ou_arr IS ARRAY(NATURAL RANGE <>) OF t_tech_ddr_phy_ou;
-- PHY address signal record
TYPE t_tech_ddr_addr IS RECORD TYPE t_tech_ddr_addr IS RECORD
chip : STD_LOGIC_VECTOR(ceil_log2(c_tech_ddr_phy.cs_w) -1 DOWNTO 0); -- Use ceil_log2() because the controller interprets the chip address as logical address (NOT individual chip select lines) chip : STD_LOGIC_VECTOR(ceil_log2(c_tech_ddr_max.cs_w) -1 DOWNTO 0); -- Use ceil_log2() because the controller interprets the chip address as logical address (NOT individual chip select lines)
bank : STD_LOGIC_VECTOR( c_tech_ddr_phy.ba_w -1 DOWNTO 0); bank : STD_LOGIC_VECTOR( c_tech_ddr_max.ba_w -1 DOWNTO 0);
row : STD_LOGIC_VECTOR( c_tech_ddr_phy.a_row_w-1 DOWNTO 0); row : STD_LOGIC_VECTOR( c_tech_ddr_max.a_row_w-1 DOWNTO 0);
column : STD_LOGIC_VECTOR( c_tech_ddr_phy.a_col_w-1 DOWNTO 0); column : STD_LOGIC_VECTOR( c_tech_ddr_max.a_col_w-1 DOWNTO 0);
END RECORD; END RECORD;
TYPE t_tech_ddr_addr_arr IS ARRAY(NATURAL RANGE <>) OF t_tech_ddr_addr; TYPE t_tech_ddr_addr_arr IS ARRAY(NATURAL RANGE <>) OF t_tech_ddr_addr;
TYPE t_c_tech_ddr_ctlr IS RECORD -- DDR3
rsl : NATURAL; -- = 4 = 2 (use both PHY clock edges) * 2 (PHY transfer at double rate), resolution
rsl_w : NATURAL; -- = 2 = ceil_log2(rsl)
address_w : NATURAL; -- = 32 = (2**32)*c_tech_ddr_phy.dq_w/c_byte_w bytes
data_w : NATURAL; -- = 256 = rsl * c_tech_ddr_phy.dq_w
maxburstsize : NATURAL; -- = 64
maxburstsize_w : NATURAL; -- = 7 = ceil_log2(maxburstsize+1)
END RECORD;
CONSTANT c_tech_ddr_ctlr : t_c_tech_ddr_ctlr := (4, 2, 32, 256, 64, 7);
CONSTANT c_tech_ddr_ctrl_nof_latent_reads : NATURAL := 100; -- Due to having a command cue, even after de-asserting read requests, the PHY keeps processing the cued read requests. CONSTANT c_tech_ddr_ctrl_nof_latent_reads : NATURAL := 100; -- Due to having a command cue, even after de-asserting read requests, the PHY keeps processing the cued read requests.
-- This makes sure 100 words are still available in the read FIFO after it de-asserted its siso.ready signal towards the ddr3 read side. -- This makes sure 100 words are still available in the read FIFO after it de-asserted its siso.ready signal towards the ddr3 read side.
CONSTANT c_tech_ddr_addr_lo : t_tech_ddr_addr := ((OTHERS=>'0'), (OTHERS=>'0'), (OTHERS=>'0'), (OTHERS=>'0')); CONSTANT c_tech_ddr_addr_lo : t_tech_ddr_addr := ((OTHERS=>'0'), (OTHERS=>'0'), (OTHERS=>'0'), (OTHERS=>'0'));
CONSTANT c_tech_ddr_addr_hi_4gb : t_tech_ddr_addr := ((OTHERS=>'1'), (OTHERS=>'1'), (OTHERS=>'1'), TO_UVEC(2**c_tech_ddr_phy_4g.a_col_w - c_tech_ddr_ctlr.rsl, c_tech_ddr_phy_4g.a_col_w)); CONSTANT c_tech_ddr_addr_hi_4gb_800m : t_tech_ddr_addr := ((OTHERS=>'1'), (OTHERS=>'1'), (OTHERS=>'1'), TO_UVEC(2**c_tech_ddr_4g_800m.a_col_w - c_tech_ddr_4g_800m.rsl, c_tech_ddr_4g_800m.a_col_w));
CONSTANT c_tech_ddr_addr_hi_sim : t_tech_ddr_addr := ((OTHERS=>'0'), (OTHERS=>'0'), TO_UVEC(3, c_tech_ddr_phy.a_row_w), TO_UVEC(2**c_tech_ddr_phy_4g.a_col_w - c_tech_ddr_ctlr.rsl, c_tech_ddr_phy_4g.a_col_w)); CONSTANT c_tech_ddr_addr_hi_sim : t_tech_ddr_addr := ((OTHERS=>'0'), (OTHERS=>'0'), TO_UVEC(3, c_tech_ddr_4g_800m.a_row_w), TO_UVEC(2**c_tech_ddr_4g_800m.a_col_w - c_tech_ddr_4g_800m.rsl, c_tech_ddr_4g_800m.a_col_w));
-- PHY MM access signal record
TYPE t_tech_ddr_miso IS RECORD TYPE t_tech_ddr_miso IS RECORD
rddata : STD_LOGIC_VECTOR(c_tech_ddr_ctlr.data_w-1 DOWNTO 0); rddata : STD_LOGIC_VECTOR(c_tech_ddr_max.data_w-1 DOWNTO 0);
rdval : STD_LOGIC; rdval : STD_LOGIC;
waitrequest_n : STD_LOGIC; waitrequest_n : STD_LOGIC;
END RECORD; END RECORD;
TYPE t_tech_ddr_mosi IS RECORD TYPE t_tech_ddr_mosi IS RECORD
address : STD_LOGIC_VECTOR(c_tech_ddr_ctlr.address_w-1 DOWNTO 0); address : STD_LOGIC_VECTOR(c_tech_ddr_max.address_w-1 DOWNTO 0);
wrdata : STD_LOGIC_VECTOR(c_tech_ddr_ctlr.data_w-1 DOWNTO 0); wrdata : STD_LOGIC_VECTOR(c_tech_ddr_max.data_w-1 DOWNTO 0);
wr : STD_LOGIC; wr : STD_LOGIC;
rd : STD_LOGIC; rd : STD_LOGIC;
burstbegin : STD_LOGIC; burstbegin : STD_LOGIC;
burstsize : STD_LOGIC_VECTOR(c_tech_ddr_ctlr.maxburstsize_w-1 DOWNTO 0); burstsize : STD_LOGIC_VECTOR(c_tech_ddr_max.maxburstsize_w-1 DOWNTO 0);
END RECORD; END RECORD;
END tech_ddr_pkg; END tech_ddr_pkg;
......
libraries/technology/ddr3/tech_ddr3.vhd
+ 2
− 4
View file @ 3c8fc0e5
...@@ -29,9 +29,7 @@ USE tech_ddr_lib.tech_ddr_pkg.ALL; ...@@ -29,9 +29,7 @@ USE tech_ddr_lib.tech_ddr_pkg.ALL;
ENTITY tech_ddr3 IS ENTITY tech_ddr3 IS
GENERIC ( GENERIC (
g_technology : NATURAL := c_tech_select_default; g_technology : NATURAL := c_tech_select_default;
g_master : BOOLEAN := TRUE; g_ddr : t_c_tech_ddr
g_ddr_phy : t_c_tech_ddr_phy;
g_ddr_ctlr : t_c_tech_ddr_ctlr
); );
PORT ( PORT (
-- PLL reference clock -- PLL reference clock
...@@ -63,7 +61,7 @@ BEGIN ...@@ -63,7 +61,7 @@ BEGIN
gen_ip_stratixiv : IF g_technology=c_tech_stratixiv GENERATE gen_ip_stratixiv : IF g_technology=c_tech_stratixiv GENERATE
u0 : ENTITY work.tech_ddr3_stratixiv u0 : ENTITY work.tech_ddr3_stratixiv
GENERIC MAP (g_master, g_ddr_phy, g_ddr_ctlr) GENERIC MAP (g_ddr)
PORT MAP (ctlr_ref_clk, ctlr_ref_rst, PORT MAP (ctlr_ref_clk, ctlr_ref_rst,
ctlr_gen_clk, ctlr_gen_rst, ctlr_gen_clk_2x, ctlr_gen_rst_2x, ctlr_gen_clk, ctlr_gen_rst, ctlr_gen_clk_2x, ctlr_gen_rst_2x,
ctlr_init_done, ctlr_init_done,
......
libraries/technology/ddr3/tech_ddr3_stratixiv.vhd
+ 93
− 95
View file @ 3c8fc0e5
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