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RTSD
HDL
Commits
bc5e1243
Commit
bc5e1243
authored
10 years ago
by
Eric Kooistra
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Added ddr3 memory model for simulation. The model comes from an example design in ip_stratixiv
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libraries/technology/ddr/tech_ddr_mem_model.vhd
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libraries/technology/ddr/tech_ddr_mem_model.vhd
libraries/technology/ddr/tech_ddr_mem_model_component_pkg.vhd
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...aries/technology/ddr/tech_ddr_mem_model_component_pkg.vhd
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