Moved ddr3/ VHDL files to ddr/hdllib.cfg. Deleted ddr3/.

libraries/technology/ddr/hdllib.cfg

@@ -8,5 +8,8 @@ build_dir_synth = $HDL_BUILD_DIR
 
 synth_files =
     tech_ddr_pkg.vhd
+    tech_ddr_component_pkg.vhd
+    tech_ddr_stratixiv.vhd
+    tech_ddr.vhd
 
 test_bench_files =

libraries/technology/ddr3/hdllib.cfg

-hdl_lib_name = tech_ddr3
-hdl_library_clause_name = tech_ddr3_lib
-hdl_lib_uses = technology tech_ddr ip_stratixiv_ddr3_uphy_4g_800_master ip_stratixiv_ddr3_uphy_4g_800_slave common
-hdl_lib_technology = 
-
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
-synth_files =
-    tech_ddr3_component_pkg.vhd
-    tech_ddr3_stratixiv.vhd
-    tech_ddr3.vhd
-
-test_bench_files =
-
-modelsim_search_libraries =
-    altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver twentynm_ver twentynm_hssi_ver twentynm_hip_ver
-    altera     lpm     sgate     altera_mf     altera_lnsim     twentynm     twentynm_hssi     twentynm_hip