Commits · f52fc96d8b9ccac2d7023e13c6e4b225cac41c09 · RTSD / HDL · GitLab

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Jan 05, 2015
- Added io_ddr_cross_domain.vhd to handle dvr_clk and ctlr_clk domains in case... · f52fc96d
  Eric Kooistra authored Jan 5, 2015
  f52fc96d
- Renamed wr_flush_en into ctlr_wr_flush_en. · 53a97fb1
  Eric Kooistra authored Jan 5, 2015
  
  53a97fb1
- Added purpose and description. · b7ad1c0d
  Eric Kooistra authored Jan 5, 2015
  
  b7ad1c0d
- Renamed wr_flush into wr_flush_en. Added purpose and description block diagram. · 60a58c37
  Eric Kooistra authored Jan 5, 2015
  
  60a58c37
- Rename wr_flush into wr_flush_en. · 9a98b562
  Eric Kooistra authored Jan 5, 2015
  
  9a98b562
Dec 23, 2014
- Support g_wr_flush_mode = VAL, SOP, SYN. · 2b15c467
  Eric Kooistra authored Dec 23, 2014
  
  2b15c467
- Added dvr_wr_fifo_usedw output for monitoring purposes, eg. used for verification in tb_io_ddr.vhd. · 0769c3b1
  Eric Kooistra authored Dec 23, 2014
  
  0769c3b1
- Use same string lenght for all g_mode options, to avoid warning on always... · 46cce982
  Eric Kooistra authored Dec 23, 2014
  46cce982
- Redefined write flush modes. Now the flush is still under control by... · 122facc2
  Eric Kooistra authored Dec 23, 2014
  122facc2
- Moved cur_addr close to where it is used. · 13071b9e
  Eric Kooistra authored Dec 23, 2014
  
  13071b9e
- Clarified clock domains and use ctlr_clk_out and ctlr_clk_in to make ctlr_clk... · 3516f313
  Eric Kooistra authored Dec 23, 2014
  3516f313
- Reordered ports. · 0c866450
  Eric Kooistra authored Dec 23, 2014
  
  0c866450
Dec 22, 2014
- Use 'RANGE instead of g_wr_fifo_depth to know width of wr_fifo_usedw. · e92d0677
  Eric Kooistra authored Dec 22, 2014
  
  e92d0677
- Use mosi/miso and sosi/siso records on the ports. · ab127a62
  Eric Kooistra authored Dec 22, 2014
  
  ab127a62
- Use mosi/miso and sosi/siso records on the ports. · 6bda9022
  Eric Kooistra authored Dec 22, 2014
  
  6bda9022
- Prepare for DDR mosi/miso ports by adding ports ctlr_rddata,rdval and ctlr_address,wrdata. · c157ca31
  Eric Kooistra authored Dec 22, 2014
  
  c157ca31
- Prepare for DDR mosi/miso ports by adding ports ctlr_rddata,rdval and ctlr_address,wrdata. · 7383de11
  Eric Kooistra authored Dec 22, 2014
  
  7383de11
- use func_tech_ddr_dq_address() for end_address, start_address and for cur_addr. · 45dea166
  Eric Kooistra authored Dec 22, 2014
  
  45dea166
- Use func_tech_ddr_ctrl_address() for ctlr_mosi.address. · 16ad05ed
  Eric Kooistra authored Dec 22, 2014
  
  16ad05ed
Dec 19, 2014
- Instantiate tech_ddr_lib.tech_ddr. Keep ctlr_gen_clk internal.diff · 87345d92
  Eric Kooistra authored Dec 19, 2014
  
  87345d92
- Added IEEE.NUMERIC_STD.ALL needed for unsigned(). · aee1a240
  Eric Kooistra authored Dec 19, 2014
  
  aee1a240
- Added IEEE.NUMERIC_STD.ALL needed for unsigned(). · 42945002
  Eric Kooistra authored Dec 19, 2014
  
  42945002
Dec 18, 2014
- Ported $UNB ddr3_flush_ctrl.vhd to $RADIOHDL io_ddr_driver_flush_ctrl.vhd.... · ee7bcfc3
  Eric Kooistra authored Dec 18, 2014
  ee7bcfc3
- Ported $UNB ddr3.vhd to $RADIOHDL io_ddr.vhd. Initial version, still needs to... · f894602f
  Eric Kooistra authored Dec 18, 2014
  f894602f