Improved stimuli using generics and functions to define the write and read block accesses. Distinghuis between tests for DDR3 and DDR4, because DDR4 model simulates about 20x slower.

- Added io_ddr to the testbench after removing it from the DUT. 

-Updated port map to interface with external io_ddr

- Added tech generics
- Removed old ddr3 generics
- Updated porttypes
- replaced ddr3 by io_ddr

-Changed all ddr3 references to io_ddr
-Renamed and removed some portnames
-CHanged the ouptut definition of address and burstsize  

The IP is generated with  --allow-mixed-language-simulation option, this affects the paths in the msim_setup.tcl and therefore the compile_ip.tcl

The IP is generated with  --allow-mixed-language-simulation option, this affects the paths in the msim_setup.tcl and therefore the compile_ip.tcl