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libraries/base/reorder/src/vhdl/reorder_transpose.vhd

@@ -20,6 +20,50 @@
 --
 --------------------------------------------------------------------------------
 
+-- Purpose: Performing a transpose (reordering data) on one or more streaming 
+--          inputs using external memory.
+--
+-- Description: The input of multiple streams (g_nof_streams) is concatenated into a 
+--              single stream. Either the data field or the complex fields can be 
+--              used, based on the g_use_complex generic.
+-- 
+--              Data on this single stream is than transposed according to the settings 
+--              of g_frame_size_in and g_reorder_seq. 
+--              The actual transpose is divided in two stages. The first stage (pre_transpose) 
+--              is done using a subband select module (reorder_col in RadioHDL).
+--              The second stage is done in external memory (DDR3, DDR4,...). 
+--         
+--              Stage 1: Pre Transpose 
+--              This stage is used to reorder data with a resolution as high as a single 
+--              sample, because the second stage (if using DDR3 for instance) has a resolution
+--              of 16 or more samples. The ss_ss_transp mm interface can be used to specify
+--              the desired reordering for the pre transpose. 
+--
+--              Stage 2: Reorder Sequencer
+--              After the pre transpose the data is send to the external memory 
+--              interface (to_mem_src_out). The reorder sequencer module provides the address
+--              and control signals for the external memory. Writing and reading is done in a 
+--              alternating way. Data from the external memory is received via the 
+--              from_mem_snk_in interface. The sequencers rhythm is based on the settings of 
+--              the g_reorder_seq generic.  
+-- 
+--              At the output the data from the single stream is split up in the original 
+--              g_nof_streams again. A block_gen module is used to generate the SYNC, SOP and EOP 
+--              signals. 
+--  
+--              SYNC and BSN
+--              At the input the BSN number at every SYNC is written to a fifo. This BSN number
+--              is inserted in the output data again when a SYNC is applied at the output. 
+-- 
+--              SYNC Period
+--              The SYNC period (the number of blocks per sync interval) is monitored with a counter.
+--              In case the number of blocks within a syncperiod is not equal to the specified 
+--              g_nof_blk_per_sync the sequencer will reset and start again when the number of 
+--              received blocksdoes match the g_nof_blk_per_sync. 
+--
+-- Remarks:
+
+
 LIBRARY IEEE, common_lib, dp_lib, io_ddr_lib, tech_ddr_lib;                   
 USE IEEE.STD_LOGIC_1164.ALL;    
 USE IEEE.numeric_std.ALL;