svn copy from unb2_minimal

boards/uniboard2/designs/unb2_test/doc/README

+Quick steps to compile and use design [unb2_minimal] in RadionHDL
+-----------------------------------------------------------------
+
+
+
+Start with the Oneclick Commands:
+    python $RADIOHDL/tools/oneclick/base/modelsim_config.py -t ip_arria10
+    python $RADIOHDL/tools/oneclick/base/quartus_config.py -t ip_arria10
+
+Generate MMM for QSYS:
+    run_qsys unb2 unb2_minimal
+
+-> From here either continue to Modelsim (simulation) or Quartus (synthesis)
+
+Simulation
+----------
+Modelsim instructions:
+    # in bash do:
+    rm $UNB/Software/python/sim/* # (optional)
+    run_modelsim unb2
+
+    # in Modelsim do:
+    lp unb2_minimal
+    mk all
+    # now double click on testbench file
+    as 10
+    run 500us
+
+    # while the simulation runs... in another bash session do:
+    cd unb2_minimal/tb/python
+    python tc_unb2_minimal.py --sim --unb 0 --bn 3 --seq INFO,PPSH,SENSORS 
+
+    # (sensor results only show up after 1000us of simulation runtime)
+
+    # to end simulation in Modelsim do:
+    quit -sim
+
+
+Synthesis
+---------
+Quartus instructions (for QSYS):
+    run_app unb2 unb2_minimal use=gen2
+    run_qcomp unb2 unb2_minimal
+
+In case of needing the Quartus GUI:
+    run_quartus unb2
+
+
+Convert .sof to .rbf:
+    # assuming in /tmp/temp_options_file: Bitstream_compression=on
+    run_rbf unb2 unb2_minimal  # QSYS
+
+
+Send to LCU capture5:
+    scp $RADIOHDL/build/quartus/unb2_minimal/unb2_minimal.rbf capture5:~/rbf/  # QSYS
+
+    # Now login on capture5 and use pythonscript to program flash:
+    cd unb2_minimal/tb/python
+
+    # for example use frontnode 0 on uniboard 0:
+    python tc_unb2_minimal.py --gn 0 --seq REGMAP,FLASH -s ~/rbf/unb2_minimal.rbf   # QSYS
+
+    python tc_unb2_minimal.py --gn 0 --seq REMU,REGMAP,INFO,PPSH,SENSORS  # start design, read info-ppsh-sensors
+

boards/uniboard2/designs/unb2_test/hdllib.cfg

+hdl_lib_name = unb2_minimal
+hdl_library_clause_name = unb2_minimal_lib
+hdl_lib_uses = common mm unb2_board 
+hdl_lib_technology = ip_arria10
+
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
+
+synth_files =
+    src/vhdl/qsys_unb2_minimal_pkg.vhd
+    src/vhdl/mmm_unb2_minimal.vhd
+    src/vhdl/unb2_minimal.vhd
+    
+test_bench_files = 
+    tb/vhdl/tb_unb2_minimal.vhd
+
+synth_top_level_entity =
+
+quartus_copy_files =
+    quartus/qsys_unb2_minimal.qsys .
+
+quartus_qsf_files =
+    $RADIOHDL/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
+
+quartus_tcl_files =
+    quartus/unb2_minimal_pins.tcl
+
+quartus_vhdl_files = 
+
+quartus_qip_files =
+    $HDL_BUILD_DIR/quartus/unb2_minimal/qsys_unb2_minimal/synthesis/qsys_unb2_minimal.qip
+
+
+# vsim -L ... -L ... ...
+modelsim_search_libraries =
+    altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver twentynm_ver twentynm_hssi_ver twentynm_hip_ver
+    altera     lpm     sgate     altera_mf     altera_lnsim     twentynm     twentynm_hssi     twentynm_hip
+

boards/uniboard2/designs/unb2_test/quartus/unb2_test_pins.tcl

+###############################################################################
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+###############################################################################
+
+#source $::env(RADIOHDL)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_all_pins.tcl
+source $::env(RADIOHDL)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_minimal_pins.tcl

boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2013
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, unb2_board_lib, mm_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE unb2_board_lib.unb2_board_pkg.ALL;
+USE unb2_board_lib.unb2_board_peripherals_pkg.ALL;
+USE mm_lib.mm_file_pkg.ALL;
+USE mm_lib.mm_file_unb_pkg.ALL;
+USE work.qsys_unb2_minimal_pkg.ALL;
+
+
+ENTITY mmm_unb2_minimal IS
+  GENERIC (
+    g_sim         : BOOLEAN := FALSE; --FALSE: use SOPC; TRUE: use mm_file I/O
+    g_sim_unb_nr  : NATURAL := 0;
+    g_sim_node_nr : NATURAL := 0
+  );
+  PORT (
+    mm_rst                   : IN  STD_LOGIC;
+    mm_clk                   : IN  STD_LOGIC;
+
+    pout_wdi                 : OUT STD_LOGIC;
+                             
+    -- Manual WDI override
+    reg_wdi_mosi             : OUT t_mem_mosi;
+    reg_wdi_miso             : IN  t_mem_miso;
+                             
+    -- system_info
+    reg_unb_system_info_mosi : OUT t_mem_mosi;
+    reg_unb_system_info_miso : IN  t_mem_miso;
+    rom_unb_system_info_mosi : OUT t_mem_mosi;
+    rom_unb_system_info_miso : IN  t_mem_miso;
+                             
+    -- UniBoard I2C sensors
+    reg_unb_sens_mosi        : OUT t_mem_mosi; 
+    reg_unb_sens_miso        : IN  t_mem_miso; 
+                             
+    -- PPSH
+    reg_ppsh_mosi            : OUT t_mem_mosi; 
+    reg_ppsh_miso            : IN  t_mem_miso; 
+                             
+    -- eth1g
+    eth1g_tse_mosi           : OUT t_mem_mosi;  
+    eth1g_tse_miso           : IN  t_mem_miso;  
+    eth1g_reg_mosi           : OUT t_mem_mosi;  
+    eth1g_reg_miso           : IN  t_mem_miso;  
+    eth1g_reg_interrupt      : IN  STD_LOGIC; 
+    eth1g_ram_mosi           : OUT t_mem_mosi;  
+    eth1g_ram_miso           : IN  t_mem_miso;
+    -- EPCS read
+    reg_dpmm_data_mosi       : OUT t_mem_mosi;
+    reg_dpmm_data_miso       : IN  t_mem_miso;
+    reg_dpmm_ctrl_mosi       : OUT t_mem_mosi;
+    reg_dpmm_ctrl_miso       : IN  t_mem_miso;
+
+    -- EPCS write
+    reg_mmdp_data_mosi       : OUT t_mem_mosi;
+    reg_mmdp_data_miso       : IN  t_mem_miso;
+    reg_mmdp_ctrl_mosi       : OUT t_mem_mosi;
+    reg_mmdp_ctrl_miso       : IN  t_mem_miso;
+
+    -- EPCS status/control
+    reg_epcs_mosi            : OUT t_mem_mosi;
+    reg_epcs_miso            : IN  t_mem_miso;
+
+    -- Remote Update
+    reg_remu_mosi            : OUT t_mem_mosi;
+    reg_remu_miso            : IN  t_mem_miso
+  );
+END mmm_unb2_minimal;
+
+ARCHITECTURE str OF mmm_unb2_minimal IS
+
+  CONSTANT c_sim_node_nr   : NATURAL := g_sim_node_nr;
+  CONSTANT c_sim_node_type : STRING(1 TO 2):= "FN";
+
+  ----------------------------------------------------------------------------
+  -- mm_file component
+  ----------------------------------------------------------------------------
+  COMPONENT mm_file
+  GENERIC(
+    g_file_prefix       : STRING;
+    g_update_on_change  : BOOLEAN := FALSE;
+    g_mm_rd_latency     : NATURAL := 1
+  );
+  PORT (
+    mm_rst        : IN  STD_LOGIC;
+    mm_clk        : IN  STD_LOGIC;
+    mm_master_out : OUT t_mem_mosi;
+    mm_master_in  : IN  t_mem_miso 
+  );
+  END COMPONENT;
+
+BEGIN
+
+  ----------------------------------------------------------------------------
+  -- MM <-> file I/O for simulation. The files are created in $UPE/sim.
+  ----------------------------------------------------------------------------
+  gen_mm_file_io : IF g_sim = TRUE GENERATE
+
+    u_mm_file_reg_unb_system_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
+                                               PORT MAP(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
+
+    u_mm_file_rom_unb_system_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
+                                               PORT MAP(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+
+    u_mm_file_reg_wdi             : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
+                                               PORT MAP(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
+
+    u_mm_file_reg_unb_sens        : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
+                                               PORT MAP(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+
+    u_mm_file_reg_ppsh            : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
+                                               PORT MAP(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+
+    -- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
+    u_mm_file_reg_eth             : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
+                                               PORT MAP(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
+
+    ----------------------------------------------------------------------------
+    -- Procedure that polls a sim control file that can be used to e.g. get
+    -- the simulation time in ns
+    ----------------------------------------------------------------------------
+    mmf_poll_sim_ctrl_file(c_mmf_unb_file_path & "sim.ctrl", c_mmf_unb_file_path & "sim.stat");
+
+  END GENERATE;
+
+  ----------------------------------------------------------------------------
+  -- QSYS for synthesis
+  ----------------------------------------------------------------------------
+  gen_qsys : IF g_sim = FALSE GENERATE
+    u_qsys : qsys_unb2_minimal
+    PORT MAP (
+
+      clk_clk                                   => mm_clk,
+      reset_reset_n                             => mm_rst,
+
+      pio_debug_wave_external_connection_export => OPEN,
+
+      -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb2_board.
+      pio_wdi_external_connection_export        => pout_wdi,
+
+      avs_eth_0_reset_export                    => OPEN,
+      avs_eth_0_clk_export                      => OPEN,
+      avs_eth_0_tse_address_export              => eth1g_tse_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_tse_adr_w-1 DOWNTO 0),
+      avs_eth_0_tse_write_export                => eth1g_tse_mosi.wr,
+      avs_eth_0_tse_read_export                 => eth1g_tse_mosi.rd,
+      avs_eth_0_tse_writedata_export            => eth1g_tse_mosi.wrdata(c_word_w-1 DOWNTO 0),
+      avs_eth_0_tse_readdata_export             => eth1g_tse_miso.rddata(c_word_w-1 DOWNTO 0),
+      avs_eth_0_tse_waitrequest_export          => eth1g_tse_miso.waitrequest,
+      avs_eth_0_reg_address_export              => eth1g_reg_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_eth_adr_w-1 DOWNTO 0),
+      avs_eth_0_reg_write_export                => eth1g_reg_mosi.wr,
+      avs_eth_0_reg_read_export                 => eth1g_reg_mosi.rd,
+      avs_eth_0_reg_writedata_export            => eth1g_reg_mosi.wrdata(c_word_w-1 DOWNTO 0),
+      avs_eth_0_reg_readdata_export             => eth1g_reg_miso.rddata(c_word_w-1 DOWNTO 0),
+      avs_eth_0_ram_address_export              => eth1g_ram_mosi.address(c_unb2_board_peripherals_mm_reg_default.ram_eth_adr_w-1 DOWNTO 0),
+      avs_eth_0_ram_write_export                => eth1g_ram_mosi.wr,
+      avs_eth_0_ram_read_export                 => eth1g_ram_mosi.rd,
+      avs_eth_0_ram_writedata_export            => eth1g_ram_mosi.wrdata(c_word_w-1 DOWNTO 0),
+      avs_eth_0_ram_readdata_export             => eth1g_ram_miso.rddata(c_word_w-1 DOWNTO 0),
+      avs_eth_0_irq_export                      => eth1g_reg_interrupt,
+
+      reg_unb_sens_reset_export                 => OPEN,
+      reg_unb_sens_clk_export                   => OPEN,
+      reg_unb_sens_address_export               => reg_unb_sens_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_unb_sens_adr_w-1 DOWNTO 0),
+      reg_unb_sens_write_export                 => reg_unb_sens_mosi.wr,
+      reg_unb_sens_writedata_export             => reg_unb_sens_mosi.wrdata(c_word_w-1 DOWNTO 0),
+      reg_unb_sens_read_export                  => reg_unb_sens_mosi.rd,
+      reg_unb_sens_readdata_export              => reg_unb_sens_miso.rddata(c_word_w-1 DOWNTO 0),
+
+      rom_system_info_reset_export              => OPEN,
+      rom_system_info_clk_export                => OPEN,
+      rom_system_info_address_export            => rom_unb_system_info_mosi.address(c_unb2_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w-1 DOWNTO 0), 
+      rom_system_info_write_export              => rom_unb_system_info_mosi.wr,
+      rom_system_info_writedata_export          => rom_unb_system_info_mosi.wrdata(c_word_w-1 DOWNTO 0),
+      rom_system_info_read_export               => rom_unb_system_info_mosi.rd,
+      rom_system_info_readdata_export           => rom_unb_system_info_miso.rddata(c_word_w-1 DOWNTO 0),
+
+      pio_system_info_reset_export              => OPEN,
+      pio_system_info_clk_export                => OPEN,
+      pio_system_info_address_export            => reg_unb_system_info_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w-1 DOWNTO 0), 
+      pio_system_info_write_export              => reg_unb_system_info_mosi.wr,
+      pio_system_info_writedata_export          => reg_unb_system_info_mosi.wrdata(c_word_w-1 DOWNTO 0),
+      pio_system_info_read_export               => reg_unb_system_info_mosi.rd,
+      pio_system_info_readdata_export           => reg_unb_system_info_miso.rddata(c_word_w-1 DOWNTO 0),
+
+      pio_pps_reset_export                      => OPEN,
+      pio_pps_clk_export                        => OPEN,
+      pio_pps_address_export                    => reg_ppsh_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_ppsh_adr_w-1),
+      pio_pps_write_export                      => reg_ppsh_mosi.wr,
+      pio_pps_writedata_export                  => reg_ppsh_mosi.wrdata(c_word_w-1 DOWNTO 0),
+      pio_pps_read_export                       => reg_ppsh_mosi.rd,
+      pio_pps_readdata_export                   => reg_ppsh_miso.rddata(c_word_w-1 DOWNTO 0),
+
+      reg_wdi_reset_export                      => OPEN,
+      reg_wdi_clk_export                        => OPEN,
+      reg_wdi_address_export                    => reg_wdi_mosi.address(0),
+      reg_wdi_write_export                      => reg_wdi_mosi.wr,
+      reg_wdi_writedata_export                  => reg_wdi_mosi.wrdata(c_word_w-1 DOWNTO 0),
+      reg_wdi_read_export                       => reg_wdi_mosi.rd,
+      reg_wdi_readdata_export                   => reg_wdi_miso.rddata(c_word_w-1 DOWNTO 0),
+
+      reg_remu_reset_export                     => OPEN,
+      reg_remu_clk_export                       => OPEN,
+      reg_remu_address_export                   => reg_remu_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_remu_adr_w-1 DOWNTO 0),
+      reg_remu_write_export                     => reg_remu_mosi.wr,
+      reg_remu_writedata_export                 => reg_remu_mosi.wrdata(c_word_w-1 DOWNTO 0),
+      reg_remu_read_export                      => reg_remu_mosi.rd,
+      reg_remu_readdata_export                  => reg_remu_miso.rddata(c_word_w-1 DOWNTO 0),
+
+      reg_epcs_reset_export                     => OPEN,
+      reg_epcs_clk_export                       => OPEN,
+      reg_epcs_address_export                   => reg_epcs_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_epcs_adr_w-1 DOWNTO 0),
+      reg_epcs_write_export                     => reg_epcs_mosi.wr,
+      reg_epcs_writedata_export                 => reg_epcs_mosi.wrdata(c_word_w-1 DOWNTO 0),
+      reg_epcs_read_export                      => reg_epcs_mosi.rd,
+      reg_epcs_readdata_export                  => reg_epcs_miso.rddata(c_word_w-1 DOWNTO 0),
+
+      reg_dpmm_ctrl_reset_export                => OPEN,
+      reg_dpmm_ctrl_clk_export                  => OPEN,
+      reg_dpmm_ctrl_address_export              => reg_dpmm_ctrl_mosi.address(0),
+      reg_dpmm_ctrl_write_export                => reg_dpmm_ctrl_mosi.wr,
+      reg_dpmm_ctrl_writedata_export            => reg_dpmm_ctrl_mosi.wrdata(c_word_w-1 DOWNTO 0),
+      reg_dpmm_ctrl_read_export                 => reg_dpmm_ctrl_mosi.rd,
+      reg_dpmm_ctrl_readdata_export             => reg_dpmm_ctrl_miso.rddata(c_word_w-1 DOWNTO 0),
+
+      reg_mmdp_data_reset_export                => OPEN,
+      reg_mmdp_data_clk_export                  => OPEN,
+      reg_mmdp_data_address_export              => reg_mmdp_data_mosi.address(0),
+      reg_mmdp_data_write_export                => reg_mmdp_data_mosi.wr,
+      reg_mmdp_data_writedata_export            => reg_mmdp_data_mosi.wrdata(c_word_w-1 DOWNTO 0),
+      reg_mmdp_data_read_export                 => reg_mmdp_data_mosi.rd,
+      reg_mmdp_data_readdata_export             => reg_mmdp_data_miso.rddata(c_word_w-1 DOWNTO 0),
+
+      reg_dpmm_data_reset_export                => OPEN,
+      reg_dpmm_data_clk_export                  => OPEN,
+      reg_dpmm_data_address_export              => reg_dpmm_data_mosi.address(0),
+      reg_dpmm_data_read_export                 => reg_dpmm_data_mosi.rd,
+      reg_dpmm_data_readdata_export             => reg_dpmm_data_miso.rddata(c_word_w-1 DOWNTO 0),
+      reg_dpmm_data_write_export                => reg_dpmm_data_mosi.wr,
+      reg_dpmm_data_writedata_export            => reg_dpmm_data_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+      reg_mmdp_ctrl_reset_export                => OPEN,
+      reg_mmdp_ctrl_clk_export                  => OPEN,
+      reg_mmdp_ctrl_address_export              => reg_mmdp_ctrl_mosi.address(0),
+      reg_mmdp_ctrl_read_export                 => reg_mmdp_ctrl_mosi.rd,
+      reg_mmdp_ctrl_readdata_export             => reg_mmdp_ctrl_miso.rddata(c_word_w-1 DOWNTO 0),
+      reg_mmdp_ctrl_write_export                => reg_mmdp_ctrl_mosi.wr,
+      reg_mmdp_ctrl_writedata_export            => reg_mmdp_ctrl_mosi.wrdata(c_word_w-1 DOWNTO 0)
+      );
+  END GENERATE;
+
+END str;

boards/uniboard2/designs/unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+PACKAGE qsys_unb2_minimal_pkg IS
+
+    -----------------------------------------------------------------------------
+    -- this component declaration is copy-pasted from Quartus v14 QSYS builder
+    -----------------------------------------------------------------------------
+
+    COMPONENT qsys_unb2_minimal is
+        port (
+            clk_clk                                   : in  std_logic                     := 'X';             -- clk
+            reset_reset_n                             : in  std_logic                     := 'X';             -- reset_n
+            pio_debug_wave_external_connection_export : out std_logic_vector(31 downto 0);                    -- export
+            pio_wdi_external_connection_export        : out std_logic;                                        -- export
+            avs_eth_0_reset_export                    : out std_logic;                                        -- export
+            avs_eth_0_clk_export                      : out std_logic;                                        -- export
+            avs_eth_0_tse_address_export              : out std_logic_vector(9 downto 0);                     -- export
+            avs_eth_0_tse_write_export                : out std_logic;                                        -- export
+            avs_eth_0_tse_read_export                 : out std_logic;                                        -- export
+            avs_eth_0_tse_writedata_export            : out std_logic_vector(31 downto 0);                    -- export
+            avs_eth_0_tse_readdata_export             : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            avs_eth_0_tse_waitrequest_export          : in  std_logic                     := 'X';             -- export
+            avs_eth_0_reg_address_export              : out std_logic_vector(3 downto 0);                     -- export
+            avs_eth_0_reg_write_export                : out std_logic;                                        -- export
+            avs_eth_0_reg_read_export                 : out std_logic;                                        -- export
+            avs_eth_0_reg_writedata_export            : out std_logic_vector(31 downto 0);                    -- export
+            avs_eth_0_reg_readdata_export             : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            avs_eth_0_ram_address_export              : out std_logic_vector(9 downto 0);                     -- export
+            avs_eth_0_ram_write_export                : out std_logic;                                        -- export
+            avs_eth_0_ram_read_export                 : out std_logic;                                        -- export
+            avs_eth_0_ram_writedata_export            : out std_logic_vector(31 downto 0);                    -- export
+            avs_eth_0_ram_readdata_export             : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            avs_eth_0_irq_export                      : in  std_logic                     := 'X';             -- export
+            reg_unb_sens_reset_export                 : out std_logic;                                        -- export
+            reg_unb_sens_clk_export                   : out std_logic;                                        -- export
+            reg_unb_sens_address_export               : out std_logic_vector(2 downto 0);                     -- export
+            reg_unb_sens_write_export                 : out std_logic;                                        -- export
+            reg_unb_sens_writedata_export             : out std_logic_vector(31 downto 0);                    -- export
+            reg_unb_sens_read_export                  : out std_logic;                                        -- export
+            reg_unb_sens_readdata_export              : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            rom_system_info_reset_export              : out std_logic;                                        -- export
+            rom_system_info_address_export            : out std_logic_vector(9 downto 0);                     -- export
+            rom_system_info_clk_export                : out std_logic;                                        -- export
+            rom_system_info_write_export              : out std_logic;                                        -- export
+            rom_system_info_writedata_export          : out std_logic_vector(31 downto 0);                    -- export
+            rom_system_info_read_export               : out std_logic;                                        -- export
+            rom_system_info_readdata_export           : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            pio_system_info_reset_export              : out std_logic;                                        -- export
+            pio_system_info_clk_export                : out std_logic;                                        -- export
+            pio_system_info_address_export            : out std_logic_vector(4 downto 0);                     -- export
+            pio_system_info_write_export              : out std_logic;                                        -- export
+            pio_system_info_writedata_export          : out std_logic_vector(31 downto 0);                    -- export
+            pio_system_info_read_export               : out std_logic;                                        -- export
+            pio_system_info_readdata_export           : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            pio_pps_reset_export                      : out std_logic;                                        -- export
+            pio_pps_clk_export                        : out std_logic;                                        -- export
+            pio_pps_address_export                    : out std_logic;--_vector(0 downto 0);                     -- export
+            pio_pps_write_export                      : out std_logic;                                        -- export
+            pio_pps_read_export                       : out std_logic;                                        -- export
+            pio_pps_writedata_export                  : out std_logic_vector(31 downto 0);                    -- export
+            pio_pps_readdata_export                   : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_wdi_reset_export                      : out std_logic;                                        -- export
+            reg_wdi_clk_export                        : out std_logic;                                        -- export
+            reg_wdi_address_export                    : out std_logic;--_vector(0 downto 0);                     -- export
+            reg_wdi_write_export                      : out std_logic;                                        -- export
+            reg_wdi_writedata_export                  : out std_logic_vector(31 downto 0);                    -- export
+            reg_wdi_read_export                       : out std_logic;                                        -- export
+            reg_wdi_readdata_export                   : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_remu_reset_export                     : out std_logic;                                        -- export
+            reg_remu_clk_export                       : out std_logic;                                        -- export
+            reg_remu_address_export                   : out std_logic_vector(2 downto 0);                     -- export
+            reg_remu_write_export                     : out std_logic;                                        -- export
+            reg_remu_writedata_export                 : out std_logic_vector(31 downto 0);                    -- export
+            reg_remu_read_export                      : out std_logic;                                        -- export
+            reg_remu_readdata_export                  : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_epcs_reset_export                     : out std_logic;                                        -- export
+            reg_epcs_clk_export                       : out std_logic;                                        -- export
+            reg_epcs_address_export                   : out std_logic_vector(2 downto 0);                     -- export
+            reg_epcs_write_export                     : out std_logic;                                        -- export
+            reg_epcs_writedata_export                 : out std_logic_vector(31 downto 0);                    -- export
+            reg_epcs_read_export                      : out std_logic;                                        -- export
+            reg_epcs_readdata_export                  : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_dpmm_ctrl_reset_export                : out std_logic;                                        -- export
+            reg_dpmm_ctrl_clk_export                  : out std_logic;                                        -- export
+            reg_dpmm_ctrl_address_export              : out std_logic;--_vector(0 downto 0);                     -- export
+            reg_dpmm_ctrl_write_export                : out std_logic;                                        -- export
+            reg_dpmm_ctrl_writedata_export            : out std_logic_vector(31 downto 0);                    -- export
+            reg_dpmm_ctrl_read_export                 : out std_logic;                                        -- export
+            reg_dpmm_ctrl_readdata_export             : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_mmdp_data_reset_export                : out std_logic;                                        -- export
+            reg_mmdp_data_clk_export                  : out std_logic;                                        -- export
+            reg_mmdp_data_address_export              : out std_logic;--_vector(0 downto 0);                     -- export
+            reg_mmdp_data_write_export                : out std_logic;                                        -- export
+            reg_mmdp_data_writedata_export            : out std_logic_vector(31 downto 0);                    -- export
+            reg_mmdp_data_read_export                 : out std_logic;                                        -- export
+            reg_mmdp_data_readdata_export             : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_mmdp_ctrl_readdata_export             : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_mmdp_ctrl_read_export                 : out std_logic;                                        -- export
+            reg_mmdp_ctrl_writedata_export            : out std_logic_vector(31 downto 0);                    -- export
+            reg_mmdp_ctrl_write_export                : out std_logic;                                        -- export
+            reg_mmdp_ctrl_address_export              : out std_logic;--_vector(0 downto 0);                     -- export
+            reg_mmdp_ctrl_clk_export                  : out std_logic;                                        -- export
+            reg_mmdp_ctrl_reset_export                : out std_logic;                                        -- export
+            reg_dpmm_data_readdata_export             : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_dpmm_data_read_export                 : out std_logic;                                        -- export
+            reg_dpmm_data_writedata_export            : out std_logic_vector(31 downto 0);                    -- export
+            reg_dpmm_data_write_export                : out std_logic;                                        -- export
+            reg_dpmm_data_address_export              : out std_logic;--_vector(0 downto 0);                     -- export
+            reg_dpmm_data_clk_export                  : out std_logic;                                        -- export
+            reg_dpmm_data_reset_export                : out std_logic                                         -- export
+        );    
+    END COMPONENT qsys_unb2_minimal;
+
+END qsys_unb2_minimal_pkg;

boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2012
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, unb2_board_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE unb2_board_lib.unb2_board_pkg.ALL;
+
+ENTITY unb2_minimal IS
+  GENERIC (
+    g_design_name : STRING  := "unb2_minimal";
+    g_design_note : STRING  := "UNUSED";
+    g_sim         : BOOLEAN := FALSE; --Overridden by TB
+    g_sim_unb_nr  : NATURAL := 0;
+    g_sim_node_nr : NATURAL := 0;
+    g_stamp_date  : NATURAL := 0;  -- Date (YYYYMMDD) -- set by QSF
+    g_stamp_time  : NATURAL := 0;  -- Time (HHMMSS)   -- set by QSF
+    g_stamp_svn   : NATURAL := 0   -- SVN revision    -- set by QSF
+  );
+  PORT (
+    -- GENERAL
+    CLK          : IN    STD_LOGIC; -- System Clock
+    PPS          : IN    STD_LOGIC; -- System Sync
+    WDI          : OUT   STD_LOGIC; -- Watchdog Clear
+    INTA         : INOUT STD_LOGIC; -- FPGA interconnect line
+    INTB         : INOUT STD_LOGIC; -- FPGA interconnect line
+
+    -- Others
+    VERSION      : IN    STD_LOGIC_VECTOR(c_unb2_board_aux.version_w-1 DOWNTO 0);
+    ID           : IN    STD_LOGIC_VECTOR(c_unb2_board_aux.id_w-1 DOWNTO 0);
+    TESTIO       : INOUT STD_LOGIC_VECTOR(c_unb2_board_aux.testio_w-1 DOWNTO 0);
+    
+    -- I2C Interface to Sensors
+    SENS_SC      : INOUT STD_LOGIC;
+    SENS_SD      : INOUT STD_LOGIC;
+  
+    -- 1GbE Control Interface
+    ETH_CLK      : IN    STD_LOGIC;
+    ETH_SGIN     : IN    STD_LOGIC_VECTOR(c_unb2_board_nof_eth-1 DOWNTO 0);
+    ETH_SGOUT    : OUT   STD_LOGIC_VECTOR(c_unb2_board_nof_eth-1 DOWNTO 0)
+  );
+END unb2_minimal;
+
+
+ARCHITECTURE str OF unb2_minimal IS
+
+  -- Firmware version x.y
+  CONSTANT c_fw_version             : t_unb2_board_fw_version := (1, 1);
+
+  -- System
+  SIGNAL cs_sim                     : STD_LOGIC;
+  SIGNAL xo_ethclk                  : STD_LOGIC;
+  SIGNAL xo_rst                   : STD_LOGIC;
+  SIGNAL xo_rst_n                 : STD_LOGIC;
+  SIGNAL mm_clk                     : STD_LOGIC;
+  SIGNAL mm_rst                     : STD_LOGIC;
+  
+  SIGNAL st_rst                     : STD_LOGIC;
+  SIGNAL st_clk                     : STD_LOGIC;
+
+  -- PIOs
+  SIGNAL pout_wdi                   : STD_LOGIC;
+
+  -- WDI override
+  SIGNAL reg_wdi_mosi               : t_mem_mosi;
+  SIGNAL reg_wdi_miso               : t_mem_miso;
+
+  -- PPSH
+  SIGNAL reg_ppsh_mosi              : t_mem_mosi;
+  SIGNAL reg_ppsh_miso              : t_mem_miso;
+  
+  -- UniBoard system info
+  SIGNAL reg_unb_system_info_mosi   : t_mem_mosi;
+  SIGNAL reg_unb_system_info_miso   : t_mem_miso;
+  SIGNAL rom_unb_system_info_mosi   : t_mem_mosi;
+  SIGNAL rom_unb_system_info_miso   : t_mem_miso;
+
+  -- UniBoard I2C sens
+  SIGNAL reg_unb_sens_mosi          : t_mem_mosi;
+  SIGNAL reg_unb_sens_miso          : t_mem_miso;
+
+  -- eth1g
+  SIGNAL eth1g_tse_mosi             : t_mem_mosi;  -- ETH TSE MAC registers
+  SIGNAL eth1g_tse_miso             : t_mem_miso;
+  SIGNAL eth1g_reg_mosi             : t_mem_mosi;  -- ETH control and status registers
+  SIGNAL eth1g_reg_miso             : t_mem_miso;
+  SIGNAL eth1g_reg_interrupt        : STD_LOGIC;   -- Interrupt
+  SIGNAL eth1g_ram_mosi             : t_mem_mosi;  -- ETH rx frame and tx frame memory
+  SIGNAL eth1g_ram_miso             : t_mem_miso;
+
+  -- EPCS read
+  SIGNAL reg_dpmm_data_mosi         : t_mem_mosi;
+  SIGNAL reg_dpmm_data_miso         : t_mem_miso;
+  SIGNAL reg_dpmm_ctrl_mosi         : t_mem_mosi;
+  SIGNAL reg_dpmm_ctrl_miso         : t_mem_miso;
+
+  -- EPCS write
+  SIGNAL reg_mmdp_data_mosi         : t_mem_mosi;
+  SIGNAL reg_mmdp_data_miso         : t_mem_miso;
+  SIGNAL reg_mmdp_ctrl_mosi         : t_mem_mosi;
+  SIGNAL reg_mmdp_ctrl_miso         : t_mem_miso;
+
+  -- EPCS status/control
+  SIGNAL reg_epcs_mosi              : t_mem_mosi;
+  SIGNAL reg_epcs_miso              : t_mem_miso;
+
+  -- Remote Update
+  SIGNAL reg_remu_mosi              : t_mem_mosi;
+  SIGNAL reg_remu_miso              : t_mem_miso;
+
+BEGIN
+
+  -----------------------------------------------------------------------------
+  -- General control function
+  -----------------------------------------------------------------------------
+  u_ctrl : ENTITY unb2_board_lib.ctrl_unb2_board
+  GENERIC MAP (
+    g_sim          => g_sim,
+    g_design_name  => g_design_name,
+    g_design_note  => g_design_note,
+    g_stamp_date   => g_stamp_date,
+    g_stamp_time   => g_stamp_time, 
+    g_stamp_svn    => g_stamp_svn, 
+    g_fw_version   => c_fw_version,
+    g_mm_clk_freq  => c_unb2_board_mm_clk_freq_50M,
+    g_eth_clk_freq => c_unb2_board_eth_clk_freq_125M,
+    g_aux          => c_unb2_board_aux
+  )
+  PORT MAP (
+    -- Clock an reset signals
+    cs_sim                   => cs_sim,
+    xo_ethclk                => xo_ethclk,
+    xo_rst                   => xo_rst,
+    xo_rst_n                 => xo_rst_n,
+
+    mm_clk                   => mm_clk,
+    mm_rst                   => mm_rst,
+
+    dp_rst                   => st_rst,
+    dp_clk                   => st_clk,
+    dp_pps                   => OPEN,
+    dp_rst_in                => st_rst,
+    dp_clk_in                => st_clk,
+    
+    -- Toggle WDI
+    pout_wdi                 => pout_wdi,
+
+    -- MM buses
+    -- REMU
+    reg_remu_mosi            => reg_remu_mosi,
+    reg_remu_miso            => reg_remu_miso,
+
+    -- EPCS read
+    reg_dpmm_data_mosi       => reg_dpmm_data_mosi,
+    reg_dpmm_data_miso       => reg_dpmm_data_miso,
+    reg_dpmm_ctrl_mosi       => reg_dpmm_ctrl_mosi,
+    reg_dpmm_ctrl_miso       => reg_dpmm_ctrl_miso,
+
+    -- EPCS write
+    reg_mmdp_data_mosi       => reg_mmdp_data_mosi,
+    reg_mmdp_data_miso       => reg_mmdp_data_miso,
+    reg_mmdp_ctrl_mosi       => reg_mmdp_ctrl_mosi,
+    reg_mmdp_ctrl_miso       => reg_mmdp_ctrl_miso,
+
+    -- EPCS status/control
+    reg_epcs_mosi            => reg_epcs_mosi,
+    reg_epcs_miso            => reg_epcs_miso,
+
+    -- . Manual WDI override
+    reg_wdi_mosi             => reg_wdi_mosi,
+    reg_wdi_miso             => reg_wdi_miso,
+    
+    -- . System_info
+    reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+    reg_unb_system_info_miso => reg_unb_system_info_miso, 
+    rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+    rom_unb_system_info_miso => rom_unb_system_info_miso, 
+    
+    -- . UniBoard I2C sensors
+    reg_unb_sens_mosi        => reg_unb_sens_mosi,
+    reg_unb_sens_miso        => reg_unb_sens_miso,    
+    
+    -- . PPSH
+    reg_ppsh_mosi            => reg_ppsh_mosi,
+    reg_ppsh_miso            => reg_ppsh_miso,
+    
+    -- eth1g
+    eth1g_tse_mosi           => eth1g_tse_mosi,
+    eth1g_tse_miso           => eth1g_tse_miso,
+    eth1g_reg_mosi           => eth1g_reg_mosi,
+    eth1g_reg_miso           => eth1g_reg_miso,
+    eth1g_reg_interrupt      => eth1g_reg_interrupt,
+    eth1g_ram_mosi           => eth1g_ram_mosi,
+    eth1g_ram_miso           => eth1g_ram_miso,
+        
+    -- FPGA pins
+    -- . General
+    CLK                      => CLK,
+    PPS                      => PPS,
+    WDI                      => WDI,
+    INTA                     => INTA,
+    INTB                     => INTB,
+    -- . Others
+    VERSION                  => VERSION,
+    ID                       => ID,
+    TESTIO                   => TESTIO,
+    -- . I2C Interface to Sensors
+    sens_sc                  => SENS_SC,
+    sens_sd                  => SENS_SD,        
+    -- . 1GbE Control Interface
+    ETH_clk                  => ETH_CLK,
+    ETH_SGIN                 => ETH_SGIN,
+    ETH_SGOUT                => ETH_SGOUT
+  );
+
+  -----------------------------------------------------------------------------
+  -- MM master
+  -----------------------------------------------------------------------------
+  u_mmm : ENTITY work.mmm_unb2_minimal
+  GENERIC MAP (
+    g_sim         => g_sim,
+    g_sim_unb_nr  => g_sim_unb_nr,
+    g_sim_node_nr => g_sim_node_nr
+   )
+  PORT MAP(  
+    mm_rst                   => mm_rst,
+    mm_clk                   => mm_clk,       
+
+    -- PIOs
+    pout_wdi                 => pout_wdi,
+
+    -- Manual WDI override
+    reg_wdi_mosi             => reg_wdi_mosi,
+    reg_wdi_miso             => reg_wdi_miso,
+
+    -- system_info
+    reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+    reg_unb_system_info_miso => reg_unb_system_info_miso,
+    rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+    rom_unb_system_info_miso => rom_unb_system_info_miso, 
+
+    -- UniBoard I2C sensors
+    reg_unb_sens_mosi        => reg_unb_sens_mosi,
+    reg_unb_sens_miso        => reg_unb_sens_miso, 
+ 
+    -- PPSH
+    reg_ppsh_mosi            => reg_ppsh_mosi,
+    reg_ppsh_miso            => reg_ppsh_miso, 
+  
+    -- eth1g
+    eth1g_tse_mosi           => eth1g_tse_mosi,
+    eth1g_tse_miso           => eth1g_tse_miso,
+    eth1g_reg_mosi           => eth1g_reg_mosi,
+    eth1g_reg_miso           => eth1g_reg_miso,
+    eth1g_reg_interrupt      => eth1g_reg_interrupt,
+    eth1g_ram_mosi           => eth1g_ram_mosi,
+    eth1g_ram_miso           => eth1g_ram_miso,
+
+    -- EPCS read
+    reg_dpmm_data_mosi       => reg_dpmm_data_mosi,
+    reg_dpmm_data_miso       => reg_dpmm_data_miso,
+    reg_dpmm_ctrl_mosi       => reg_dpmm_ctrl_mosi,
+    reg_dpmm_ctrl_miso       => reg_dpmm_ctrl_miso,
+
+    -- EPCS write
+    reg_mmdp_data_mosi       => reg_mmdp_data_mosi,
+    reg_mmdp_data_miso       => reg_mmdp_data_miso,
+    reg_mmdp_ctrl_mosi       => reg_mmdp_ctrl_mosi,
+    reg_mmdp_ctrl_miso       => reg_mmdp_ctrl_miso,
+
+    -- EPCS status/control
+    reg_epcs_mosi            => reg_epcs_mosi,
+    reg_epcs_miso            => reg_epcs_miso,
+
+    -- Remote Update
+    reg_remu_mosi            => reg_remu_mosi,
+    reg_remu_miso            => reg_remu_miso
+  );
+
+  -----------------------------------------------------------------------------
+  -- Node function
+  -----------------------------------------------------------------------------
+  -- Insert node_[design_name] here
+
+END str;
+

boards/uniboard2/designs/unb2_test/tb/python/tc_unb2_test.py

+#! /usr/bin/env python
+###############################################################################
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+###############################################################################
+
+"""Test case for unb1_minimal
+
+Usage:
+
+   --rep = number of intervals that diagnostics results are verified
+   --sim targets a running simulation.
+
+Description:
+   This test case tests:
+   - system info
+   - read sensors
+   - read ppsh
+   - write to wdi to force reload from bank 0
+   - flash access: write image to bank 1
+   - remote update: start image in bank 1
+
+"""
+
+###############################################################################
+# System imports
+import sys
+import signal
+import test_case
+import node_io
+import pi_system_info
+import pi_unb_sens
+import pi_ppsh
+import pi_wdi
+import pi_epcs
+import pi_remu
+import pi_eth
+import pi_debug_wave
+
+from tools import *
+from common import *
+from pi_common import *
+
+
+def test_info(tc,io,cmd):
+    tc.set_section_id('Read System Info - ')
+    tc.append_log(3, '>>>')
+    tc.append_log(1, '>>> %s' % help_text(tc,io,cmd))
+    tc.append_log(3, '>>>')
+
+    info = pi_system_info.PiSystemInfo(tc, io)
+    info.read_system_info()
+    tc.append_log(3, '')
+    info.read_use_phy()
+    tc.append_log(3, '')
+    design_name = info.read_design_name()
+    tc.append_log(1, '>>> design_name=%s' % design_name)
+    tc.append_log(3, '')
+    info.read_stamps()
+    tc.append_log(3, '')
+    info.read_design_note()
+    
+    expected_design_name = tc.gpString
+    if expected_design_name != '':
+        tc.set_section_id('Verify System Info - ')
+        compared=True
+        for name in design_name:
+            if (name != expected_design_name): 
+                tc.set_result('FAILED')
+                compared=False
+                tc.append_log(2, '>>> design_name mismatch!! (%s != %s)' % (name,expected_design_name))
+        tc.append_log(1, '>>> Verify design_name == %s: %s' % (expected_design_name,compared))
+
+
+
+def read_regmap(tc,io,cmd):
+    tc.set_section_id('Update REGMAP - ')
+    info = pi_system_info.PiSystemInfo(tc, io)
+    tc.append_log(1, '>>> reading REGMAPs')
+    info.make_register_info()
+    tc.append_log(1, '>>> reload NodeIO class')
+    return node_io.NodeIO(tc.nodeImages, tc.base_ip)
+
+
+    
+def test_sensors(tc,io,cmd):
+    tc.set_section_id('Read sensors - ')
+    tc.append_log(3, '>>>')
+    tc.append_log(1, '>>> %s' % help_text(tc,io,cmd))
+    tc.append_log(3, '>>>')
+    
+    sens = pi_unb_sens.PiUnbSens(tc, io)
+
+    sens.read_unb_sensors()
+    tc.append_log(3, '')
+    sens.read_fpga_temperature()
+    tc.append_log(3, '')
+    sens.read_eth_temperature()
+    tc.append_log(3, '')
+    sens.read_unb_current()
+    sens.read_unb_voltage()
+    sens.read_unb_power()
+
+
+
+def test_ppsh(tc,io,cmd):
+    tc.set_section_id('Read PPSH capture count - ')
+    tc.append_log(3, '>>>')
+    tc.append_log(1, '>>> %s' % help_text(tc,io,cmd))
+    tc.append_log(3, '>>>')
+    
+    Ppsh = pi_ppsh.PiPpsh(tc, io)
+    Ppsh.read_ppsh_capture_cnt()
+    tc.append_log(3, '')
+
+
+
+def test_wdi(tc,io,cmd):
+    tc.set_section_id('Reset to image in bank 0 using WDI - ')
+    tc.append_log(3, '>>>')
+    tc.append_log(1, '>>> %s' % help_text(tc,io,cmd))
+    tc.append_log(3, '>>>')
+
+    Wdi = pi_wdi.PiWdi(tc, io)
+    Wdi.write_wdi_override()
+    tc.append_log(3, '')
+    tc.append_log(3, '>>> Booting...')
+    tc.sleep(5.0)
+
+
+
+def test_remu(tc,io,cmd):
+    tc.set_section_id('REMU start image in bank 1 - ')
+    tc.append_log(3, '>>>')
+    tc.append_log(1, '>>> %s' % help_text(tc,io,cmd))
+    tc.append_log(3, '>>>')
+
+    dummy_tc = test_case.Testcase('Dummy TB - ', '',logfilename='REMU-log')
+    dummy_tc.set_result('PASSED')
+    
+    Remu = pi_remu.PiRemu(dummy_tc, io)
+    try:
+        Remu.write_user_reconfigure()
+    except:
+        pass # ignoring FAILED
+
+    if dummy_tc.get_result() == 'FAILED':
+        tc.append_log(1, 'Result=%s but ignoring this' % dummy_tc.get_result())
+
+    tc.append_log(3, '>>> Booting...')
+    tc.sleep(5.0)
+    tc.append_log(3, '')
+
+
+
+def test_eth(tc,io,cmd):
+    tc.set_section_id('ETH status - ')
+    tc.append_log(3, '>>>')
+    tc.append_log(1, '>>> %s' % help_text(tc,io,cmd))
+    tc.append_log(3, '>>>')
+    
+    eth = pi_eth.PiEth(tc, io)
+    hdr=eth.read_hdr(0)
+    eth.disassemble_hdr(hdr)
+    tc.append_log(3, '')
+
+
+
+def test_flash(tc,io,cmd):
+    tc.set_section_id('Flash write to bank 1 - ')
+    tc.append_log(3, '>>>')
+    tc.append_log(1, '>>> %s' % help_text(tc,io,cmd))
+    tc.append_log(3, '>>>')
+    
+    Epcs = pi_epcs.PiEpcs(tc, io)
+    path_to_rbf = instanceName = tc.gpString
+    Epcs.write_raw_binary_file("user", path_to_rbf)
+    tc.append_log(3, '')
+
+    tc.set_section_id('Flash read/verify bank 1 - ')
+    tc.append_log(3, '>>>')
+    tc.append_log(1, '>>> Read from flash (pi_epcs.py)')
+    tc.append_log(3, '>>>')
+    
+    path_to_rbf = instanceName = tc.gpString
+    Epcs.read_and_verify_raw_binary_file("user", path_to_rbf)
+    tc.append_log(3, '')
+
+
+def set_led(tc,dw,led,text):
+    tc.append_log(3, text)
+    dw.set_led(led)
+    tc.sleep(1.0)
+
+def test_leds(tc,io,cmd):
+    tc.set_section_id('LED test - ')
+    tc.append_log(3, '>>>')
+    tc.append_log(1, '>>> %s' % help_text(tc,io,cmd))
+    tc.append_log(3, '>>>')
+    dw =  pi_debug_wave.PiDebugWave(tc, io)
+    set_led(tc,dw,'off',   '')
+    set_led(tc,dw,'red',  'RED on')
+    set_led(tc,dw,'off',  'RED off')
+    set_led(tc,dw,'green','GREEN on')
+    set_led(tc,dw,'off',  'GREEN off')
+    set_led(tc,dw,'both', 'ORANGE (RED+GREEN) on')
+    set_led(tc,dw,'off',  'ORANGE (RED+GREEN) off')
+    tc.append_log(3, '')
+
+
+def sleep(tc,io,cmd):
+    tc.set_section_id('%s - ' % cmd)
+    tc.append_log(1, '>>> %s' % help_text(tc,io,cmd))
+    if cmd == 'sleep1':
+        tc.sleep(1.0)
+    elif cmd == 'sleep5':
+        tc.sleep(5.0)
+
+def show_help(tc,io,cmd):
+    tc.set_section_id('%s - ' % cmd)
+    tc.append_log(1, '>>> %s' % help_text(tc,io,cmd))
+
+
+# Avaliable commands
+Cmd = dict()
+Cmd['REGMAP']  = (read_regmap,  'using pi_system_info to read register info (access PIO_SYSTEM_INFO) and store REGMAPs','')
+Cmd['INFO']    = (test_info,    'using pi_system_info to read system info (access PIO_SYSTEM_INFO)','(-s for expected design_name)')
+Cmd['FLASH']   = (test_flash,   'using pi_epcs to program/verify flash','(-s for .rbf file)')
+Cmd['SENSORS'] = (test_sensors, 'using pi_unb_sens to readout sensors (access REG_UNB_SENS)','')
+Cmd['LED']     = (test_leds,    'using pi_debug_wave to set LEDs (access PIO_DEBUG_WAVE)','')
+Cmd['PPSH']    = (test_ppsh,    'using pi_ppsh to read PPSH capture count (access PIO_PPS)','')
+Cmd['ETH']     = (test_eth,     'using pi_eth to read eth status','')
+Cmd['REMU']    = (test_remu,    'using pi_remu to load user image (access REG_REMU)','')
+Cmd['WDI']     = (test_wdi,     'using pi_wdi to reset to image in bank 0 (access REG_WDI)','')
+Cmd['sleep1']  = (sleep,        'Sleep 1 second','')
+Cmd['sleep5']  = (sleep,        'Sleep 5 seconds','')
+Cmd['example'] = (show_help,    'show several example commands','')
+Cmd['help']    = (show_help,    'show help on commands','')
+
+
+def help_text(tc,io,cmd):
+    str=''
+    if cmd == 'help':
+        tc.append_log(0, '\n')
+        tc.append_log(0, '>>> Help:')
+        tc.append_log(0, 'Usage: %s <nodes> <command sequence> [-v..] [--rep ...]' % sys.argv[0])
+        tc.append_log(0, '')
+        tc.append_log(0, '    <nodes>: use: --unb N --fn N --bn N (N is a number or vector) or:')
+        tc.append_log(0, '    <nodes>: use: --gn N (N is a number or vector)')
+        tc.append_log(0, '    <command sequence>: use: --seq <command(s) separated by ",">:')
+        tc.append_log(0, '')
+        for cmd in sorted(Cmd):
+            tc.append_log(0, '    .  %s\t%s  %s' % (cmd,Cmd[cmd][1],Cmd[cmd][2]))
+        tc.append_log(0, '')
+        tc.append_log(0, '    [-vN]: verbose level N (default=5): %s' % tc.verbose_levels())
+        tc.append_log(0, '    [--rep N]: N=number of repeats, where -1 is forever, non-stop')
+        help_text(tc,io,'example')
+    elif cmd == 'example':
+        tc.append_log(0, '')
+        tc.append_log(0, '>>> Examples:')
+        tc.append_log(0, '')
+        tc.append_log(0, 'Getting INFO from all nodes on 1 Uniboard: %s --gn 0:7 --seq INFO' % sys.argv[0])
+        tc.append_log(0, '')
+        tc.append_log(0, '[reset, load user img] sequence: --seq REGMAP,WDI,REGMAP,REMU,REGMAP,INFO')
+        tc.append_log(0, '[flash+start user img] sequence: --seq FLASH,WDI,REGMAP,REMU,REGMAP,INFO -s file.rbf')
+        tc.append_log(0, '[re-read info,sensors] sequence: --seq INFO,PPSH,SENSORS --rep -1 -s expected_design_name')
+        tc.append_log(0, '[reset to factory]     sequence: --seq WDI,REGMAP')
+        tc.append_log(0, '[program user image]   sequence: --seq FLASH -s file.rbf')
+        tc.append_log(0, '[load user image]      sequence: --seq REMU,REGMAP')
+        tc.append_log(0, '[modelsim BG-DB test] arguments: --unb 0 --fn 0 --seq BGDB --sim -r 0:2')
+        tc.append_log(0, '\n')
+    else:
+        str = Cmd[cmd][1]
+    return str
+
+
+def signal_handler(signal, frame):
+    print('You pressed Ctrl+C!')
+    tc.repeat=0
+
+
+##################################################################################################################
+# Main
+#
+# Create a test case object
+tc = test_case.Testcase('TB - ', '')
+tc.set_result('PASSED')
+dgnName = tc.gpString
+tc.append_log(3, '>>>')
+tc.append_log(0, '>>> Title : Test bench (%s) on nodes %s, %s' % (sys.argv[0],tc.unb_nodes_string(''),dgnName))
+tc.append_log(0, '>>> Commandline : %s' % " ".join(sys.argv))
+tc.append_log(3, '>>>')
+
+
+# Create access object for nodes
+io = node_io.NodeIO(tc.nodeImages, tc.base_ip)
+
+signal.signal(signal.SIGINT, signal_handler)
+
+##################################################################################################################
+# Run tests
+while tc.repeat != 0: # -1 for non-stop
+    tc.repeat -= 1
+    tc.next_run()
+    tc.append_log(3, '')
+    
+    try:
+        for cmd in tc.sequence:
+            tc.set_section_id('Next command: %s ' % cmd)
+            tc.append_log(1, '>>> Testrun %d (@%.02fs) - ' % (tc.get_nof_runs(),tc.get_run_time()))
+
+            if cmd == 'REGMAP': # reload node_io:
+                io = Cmd[cmd][0](tc,io,cmd)
+            else:
+                Cmd[cmd][0](tc,io,cmd)
+
+
+    except KeyError:
+        print 'Unknown command:',cmd
+        cmd='help'
+        Cmd[cmd][0](tc,io,cmd)
+#    except:
+#        print 'Catched error:',sys.exc_info()[0]
+
+
+
+##################################################################################################################
+# End
+tc.set_section_id('')
+tc.append_log(3, '')
+tc.append_log(3, '>>>')
+tc.append_log(0, '>>> Test bench result: %s' % tc.get_result())
+tc.append_log(0, '>>> Number of runs=%d' % tc.get_nof_runs())
+tc.append_log(0, '>>> Number of errors=%d' % tc.get_nof_errors())
+tc.append_log(0, '>>> Runtime=%f seconds (%f hours)' % (tc.get_run_time(),tc.get_run_time()/3600))
+tc.append_log(3, '>>>')
+
+sys.exit(tc.get_result())
+

boards/uniboard2/designs/unb2_test/tb/vhdl/tb_unb2_test.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2012
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: Test bench for unb2_minimal.
+-- Description:
+--   The DUT can be targeted at unb 0, node 3 with the same Python scripts 
+--   that are used on hardware. 
+-- Usage:
+--   On command line do:
+--     > run_modelsim & (to start Modeslim)
+--
+--   In Modelsim do:
+--     > lp unb2_minimal
+--     > mk clean all (only first time to clean all libraries)
+--     > mk all (to compile all libraries that are needed for unb2_minimal)
+--     . load tb_unb1_minimal simulation by double clicking the tb_unb2_minimal icon
+--     > as 10 (to view signals in Wave Window)
+--     > run 100 us (or run -all)
+--
+--   On command line do:
+--     > python $UPE/peripherals/util_system_info.py --gn 3 -n 0 -v 5 --sim
+--     > python $UPE/peripherals/util_unb_sens.py --gn 3 -n 0 -v 5 --sim
+--     > python $UPE/peripherals/util_ppsh.py --gn 3 -n 1 -v 5 --sim
+--
+
+LIBRARY IEEE, common_lib, unb2_board_lib, i2c_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE unb2_board_lib.unb2_board_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+
+ENTITY tb_unb2_minimal IS
+    GENERIC (
+      g_design_name : STRING  := "unb2_minimal";
+      g_sim_unb_nr  : NATURAL := 0; -- UniBoard 0
+      g_sim_node_nr : NATURAL := 3  -- Node 3
+    );
+END tb_unb2_minimal;
+
+ARCHITECTURE tb OF tb_unb2_minimal IS
+
+  CONSTANT c_sim             : BOOLEAN := TRUE;
+
+  CONSTANT c_unb_nr          : NATURAL := 0; -- UniBoard 0
+  CONSTANT c_node_nr         : NATURAL := 3; -- Node 3
+  CONSTANT c_id              : STD_LOGIC_VECTOR(7 DOWNTO 0) := TO_UVEC(c_unb_nr, c_unb2_board_nof_uniboard_w) & TO_UVEC(c_node_nr, c_unb2_board_nof_chip_w);
+
+  CONSTANT c_version         : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
+  CONSTANT c_fw_version      : t_unb2_board_fw_version := (1, 0);
+
+  CONSTANT c_cable_delay     : TIME := 12 ns;
+  CONSTANT c_eth_clk_period  : TIME := 40 ns;  -- 25 MHz XO on UniBoard
+  CONSTANT c_clk_period      : TIME := 5 ns; 
+  CONSTANT c_pps_period      : NATURAL := 1000; 
+
+  -- DUT
+  SIGNAL clk                 : STD_LOGIC := '0';
+  SIGNAL pps                 : STD_LOGIC := '0';
+  SIGNAL pps_rst             : STD_LOGIC := '0';
+
+  SIGNAL WDI                 : STD_LOGIC;
+  SIGNAL INTA                : STD_LOGIC;
+  SIGNAL INTB                : STD_LOGIC;
+
+  SIGNAL eth_clk             : STD_LOGIC := '0';
+  SIGNAL eth_txp             : STD_LOGIC;
+  SIGNAL eth_rxp             : STD_LOGIC;
+  
+  SIGNAL VERSION             : STD_LOGIC_VECTOR(c_unb2_board_aux.version_w-1 DOWNTO 0) := c_version; 
+  SIGNAL ID                  : STD_LOGIC_VECTOR(c_unb2_board_aux.id_w-1 DOWNTO 0)      := c_id;
+  SIGNAL TESTIO              : STD_LOGIC_VECTOR(c_unb2_board_aux.testio_w-1 DOWNTO 0);
+
+  SIGNAL sens_scl            : STD_LOGIC;
+  SIGNAL sens_sda            : STD_LOGIC;
+
+  -- Model I2C sensor slaves as on the UniBoard
+  CONSTANT c_fpga_temp_address   : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0011000";  -- MAX1618 address LOW LOW
+  CONSTANT c_fpga_temp           : INTEGER := 60;
+  CONSTANT c_eth_temp_address    : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0101001";  -- MAX1618 address MID LOW
+  CONSTANT c_eth_temp            : INTEGER := 40;
+  CONSTANT c_hot_swap_address    : STD_LOGIC_VECTOR(6 DOWNTO 0) := "1000100";  -- LTC4260 address L L L
+  CONSTANT c_hot_swap_R_sense    : REAL := 0.01;                               -- = 10 mOhm on UniBoard
+  
+  CONSTANT c_uniboard_current    : REAL := 5.0;   -- = assume 5.0 A on UniBoard
+  CONSTANT c_uniboard_supply     : REAL := 48.0;  -- = assume 48.0 V on UniBoard
+  CONSTANT c_uniboard_adin       : REAL := -1.0;  -- = NC on UniBoard
+
+BEGIN
+
+  ----------------------------------------------------------------------------
+  -- System setup
+  ----------------------------------------------------------------------------
+  clk     <= NOT clk AFTER c_clk_period/2;        -- External clock (200 MHz)
+  eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2;  -- Ethernet ref clock (25 MHz)
+  
+  INTA <= 'H';  -- pull up
+  INTB <= 'H';  -- pull up
+
+  sens_scl <= 'H';  -- pull up
+  sens_sda <= 'H';  -- pull up
+
+  ------------------------------------------------------------------------------
+  -- External PPS
+  ------------------------------------------------------------------------------  
+  proc_common_gen_pulse(1, c_pps_period, '1', pps_rst, clk, pps);
+
+  ------------------------------------------------------------------------------
+  -- 1GbE Loopback model
+  ------------------------------------------------------------------------------  
+  eth_rxp <= TRANSPORT eth_txp AFTER c_cable_delay;
+  
+  ------------------------------------------------------------------------------
+  -- DUT
+  ------------------------------------------------------------------------------
+  u_unb2_minimal : ENTITY work.unb2_minimal
+    GENERIC MAP (
+      g_sim         => c_sim,
+      g_sim_unb_nr  => c_unb_nr,
+      g_sim_node_nr => c_node_nr,
+      g_design_name => g_design_name
+    )
+    PORT MAP (
+      -- GENERAL
+      CLK         => clk,
+      PPS         => pps,
+      WDI         => WDI,
+      INTA        => INTA,
+      INTB        => INTB,
+
+      sens_sc     => sens_scl,
+      sens_sd     => sens_sda,
+
+      -- Others
+      VERSION     => VERSION,
+      ID          => ID,
+      TESTIO      => TESTIO,
+
+      -- 1GbE Control Interface
+      ETH_clk     => eth_clk,
+      ETH_SGIN    => eth_rxp,
+      ETH_SGOUT   => eth_txp
+    );
+
+  ------------------------------------------------------------------------------
+  -- UniBoard sensors
+  ------------------------------------------------------------------------------
+  -- I2C slaves that are available for each FPGA
+  u_fpga_temp : ENTITY i2c_lib.dev_max1618
+  GENERIC MAP (
+    g_address => c_fpga_temp_address
+  )
+  PORT MAP (
+    scl  => sens_scl,
+    sda  => sens_sda,
+    temp => c_fpga_temp
+  );
+
+  -- I2C slaves that are available only via FPGA back node 3
+  u_eth_temp : ENTITY i2c_lib.dev_max1618
+  GENERIC MAP (
+    g_address => c_eth_temp_address
+  )
+  PORT MAP (
+    scl  => sens_scl,
+    sda  => sens_sda,
+    temp => c_eth_temp
+  );
+  
+  u_power : ENTITY i2c_lib.dev_ltc4260
+  GENERIC MAP (
+    g_address => c_hot_swap_address,
+    g_R_sense => c_hot_swap_R_sense
+  )
+  PORT MAP (
+    scl               => sens_scl,
+    sda               => sens_sda,
+    ana_current_sense => c_uniboard_current,
+    ana_volt_source   => c_uniboard_supply,
+    ana_volt_adin     => c_uniboard_adin
+  );
+
+END tb;