removed end_addrs

libraries/base/reorder/src/vhdl/reorder_sequencer.vhd

@@ -76,7 +76,6 @@ ARCHITECTURE rtl OF reorder_sequencer IS
     first_write      : STD_LOGIC;
     sync_ok_out      : STD_LOGIC;
     start_addr       : STD_LOGIC_VECTOR(c_address_w - 1 DOWNTO 0);
-    end_addr         : STD_LOGIC_VECTOR(c_address_w - 1 DOWNTO 0);
     burstsize        : STD_LOGIC_VECTOR(c_address_w - 1 DOWNTO 0);
     state            : state_type;  -- The state machine. 
   END RECORD;
@@ -110,7 +109,6 @@ BEGIN
         v.ddr3_en    := '1'; 
         v.start_addr := TO_UVEC(r.wr_page_offset + r.wr_block_offset + r.wr_chunks_offset, c_address_w);
         v.burstsize  := TO_UVEC(g_reorder_seq.wr_chunksize, c_address_w);
-        v.end_addr   := TO_UVEC(r.wr_page_offset + r.wr_block_offset + r.wr_chunks_offset + g_reorder_seq.wr_chunksize-4, c_address_w);  
         v.switch_cnt := r.switch_cnt + 1;
         v.state      := s_wait_wr;
         
@@ -122,7 +120,6 @@ BEGIN
           END IF;
           v.start_addr := TO_UVEC(r.wr_page_offset + r.wr_block_offset + r.wr_chunks_offset, c_address_w);                   
           v.burstsize  := TO_UVEC(g_reorder_seq.wr_chunksize, c_address_w);
-          v.end_addr   := TO_UVEC(r.wr_page_offset + r.wr_block_offset + r.wr_chunks_offset + g_reorder_seq.wr_chunksize-4, c_address_w);  
           v.switch_cnt := r.switch_cnt + 1;
           v.state      := s_wait_wr; 
         END IF;
@@ -159,7 +156,6 @@ BEGIN
           END IF; 
           v.start_addr  := TO_UVEC(r.rd_page_offset + r.rd_block_offset + r.rd_chunks_offset, c_address_w); 
           v.burstsize   := TO_UVEC(g_reorder_seq.rd_chunksize, c_address_w);
-          v.end_addr    := TO_UVEC(r.rd_page_offset + r.rd_block_offset + r.rd_chunks_offset + g_reorder_seq.rd_chunksize-4, c_address_w);   
           v.switch_cnt  := r.switch_cnt + 1; 
           v.state       := s_wait_rd;
           v.sync_ok_out := sync_ok_in;
@@ -220,7 +216,6 @@ BEGIN
       v.sync_ok_out      := '0';
       v.start_addr       := (OTHERS => '0');
       v.burstsize        := (OTHERS => '0');
-      v.end_addr         := (OTHERS => '0'); 
       v.first_write      := '1';
       v.state            := s_idle;
     END IF;