better svn revision capture based on $RADIOHDL_SVN_REVISION

boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf

@@ -61,9 +61,6 @@ set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 5P0 -section_id eda_b
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
 
 
-# Compilation flow:
-set_global_assignment -name SMART_RECOMPILE ON
-
 # Optimize for performance:
 set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED
 set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
@@ -84,6 +81,7 @@ set_global_assignment -name SDC_FILE $::env(RADIOHDL)/boards/uniboard2/libraries
 if { [info exists ::env(UNB_COMPILE_STAMPS) ] } {
   set_parameter -name g_stamp_date [clock format [clock seconds] -format {%Y%m%d}]
   set_parameter -name g_stamp_time [clock format [clock seconds] -format {%H%M%S}]
-  set_parameter -name g_stamp_svn  [regsub -all {[^0-9]} [exec svn info $::env(RADIOHDL) | grep Revision] ""]
+  post_message -type info "RADIOHDL: using SVN revision $::env(RADIOHDL_SVN_REVISION)"
+  set_parameter -name g_stamp_svn [regsub -all {[^0-9]} [exec echo $::env(RADIOHDL_SVN_REVISION)] ""] 
 }
 

tools/quartus/quartus_generic.sh

@@ -42,3 +42,4 @@ export ALTERA_HW_TCL_KEEP_TEMP_FILES=1
 
 # User synthesis timestamp in FPGA image
 export UNB_COMPILE_STAMPS=1
+export RADIOHDL_SVN_REVISION=`svn info ${RADIOHDL} | grep Revision`