Commits · e05e39801c9d47b48ca8e2b3591e6acb1d417629 · RTSD / HDL

Oct 06, 2015
- added the 10G transceivers for 48 channels per ATXPLL · e05e3980
  Kenneth Hiemstra authored 9 years ago
  
  e05e3980
Oct 01, 2015
- update · 1a94194a
  Kenneth Hiemstra authored 9 years ago
  
  1a94194a
- added the tech_ layer for the fpga temp sensor · 40dafeee
  Kenneth Hiemstra authored 9 years ago
  
  40dafeee
- added the fpga temp sensor for arria10 · 010771fc
  Kenneth Hiemstra authored 9 years ago
  
  010771fc
- fixed DDR3 IP for 16GB SO-Dimms · aa76980d
  Zanting authored 9 years ago
  
  aa76980d
Sep 30, 2015
- Changed default to stratixiv · 5adcb3c8
  Zanting authored 9 years ago
  
  5adcb3c8
- Reverted to own pll/dll for 4g single rank slave · 16a4215a
  Zanting authored 9 years ago
  
  16a4215a
- Reverted to own pll/dll for 4g single rank slave · cde216f4
  Zanting authored 9 years ago
  
  cde216f4
- IP for 16GB DDR3 So-Dimm modules added · 878ceca5
  Zanting authored 9 years ago
  
  878ceca5
- IP for 16GB DDR3 So-Dimm modules added · 4750ad20
  Zanting authored 9 years ago
  
  4750ad20
Sep 28, 2015
- IP for 16GB DDR3 So-Dimm modules added · 67c8bcec
  Zanting authored 9 years ago
  
  67c8bcec
- added DDR4 doc for IP generation · 1ddc8157
  Kenneth Hiemstra authored 9 years ago
  
  1ddc8157
- IP for 16GB DDR3 So-Dimm modules · cace6663
  Zanting authored 9 years ago
  
  cace6663
Sep 25, 2015
- fixed magic codes · 5d9e7979
  Kenneth Hiemstra authored 9 years ago
  
  5d9e7979
- cosmetic · db950540
  Kenneth Hiemstra authored 9 years ago
  
  db950540
- can choose now ddr4 1600 or 2000 · fda9eccc
  Kenneth Hiemstra authored 9 years ago
  
  fda9eccc
Sep 24, 2015
- Updated DDR3 slave IP · 428bf5d7
  Zanting authored 9 years ago
  
  428bf5d7
Sep 11, 2015
- added gluelogic for the 4x chan 10G IPs · 16ff9a6d
  Kenneth Hiemstra authored 9 years ago
  
  16ff9a6d
- added possible 10G channel configs · c066bd8f
  Kenneth Hiemstra authored 9 years ago
  
  c066bd8f
Sep 09, 2015
- deleted because correct name is ip_arria10_pll_xgmii_mac_clocks.qsys · c63d6b56
  Kenneth Hiemstra authored 9 years ago
  
  c63d6b56
Aug 29, 2015
- moved to ATXPLL driving 12 PHY's instead of 24 · e1e5d150
  Kenneth Hiemstra authored 9 years ago
  
  e1e5d150
- moved to ATXPLL driving 12 PHY's instead of 24 · c80abada
  Kenneth Hiemstra authored 9 years ago
  
  c80abada
Aug 18, 2015
- changed the ATXPLL selecting from 1-24 to 1-12. Either 1 ATXPLL will · aaf62b8f
  Kenneth Hiemstra authored 9 years ago
  
  drive 1xPHY or 1 ATXPLL will drive 12xPHY (recommented by Altera)
  aaf62b8f
- added ddr4_4g_2000 IP · 08d9a16e
  Kenneth Hiemstra authored 9 years ago
  
  08d9a16e
- 10G PHY. 12 channels driven by 1 ATXPLL · 7620fd87
  Kenneth Hiemstra authored 9 years ago
  
  7620fd87
- based on ddr4_4g_1600 but changed clock/timings · dcf1dc3b
  Kenneth Hiemstra authored 9 years ago
  
  dcf1dc3b
Aug 17, 2015
- Reverted edit in path · 45ef5f3e
  Pepping authored 9 years ago
  
  45ef5f3e
Aug 14, 2015
- Fixed qip file folder · 2535e8d7
  Zanting authored 9 years ago
  
  2535e8d7
Aug 13, 2015
- working version for DDR4 using bank mb_I and mb_II (settings are used · 08d50252
  Kenneth Hiemstra authored 9 years ago
  
  from ddr4 testing version ddr4_micron_46)
  08d50252
- changed c_tech_ddr4_max to use a dual rank DDR4 as single rank (see · e39ca9bd
  Kenneth Hiemstra authored 9 years ago
  
  CS1_n, CKE1, ODT1 in tech_ddr_arria10.vhd)
  e39ca9bd
- using a dual rank DDR4 but the IP is single rank: disabling 2nd rank by · 0e2b1046
  Kenneth Hiemstra authored 9 years ago
  
  setting CS1_n=1, CKE1=0 and ODT1=0
  0e2b1046
- Changed PLL and DLL from Slave to Master as was the case with the dual rank ddr3 slave. · debc815c
  Zanting authored 9 years ago
  
  debc815c
Aug 12, 2015
- Added copy hex files script for DDR3 slave UniPHY ip · 1131ff16
  Zanting authored 9 years ago
  
  1131ff16
Jul 16, 2015
- Removed g_link_status_check from tech_eth_10g entity. Added g_direction =... · e5b58438
  Eric Kooistra authored 9 years ago
  
  Removed g_link_status_check from tech_eth_10g entity. Added g_direction = TX_RX default or TX_ONLY, RX_ONLY. Implemented TX_ONLY by internal loopback of MAC Tx xgmii to MAX Rx.
  e5b58438
- Removed g_link_status_check from tech_eth_10g entity. · 24d5f8f2
  Eric Kooistra authored 9 years ago
  
  24d5f8f2
- Improved comment on link_fault. · 797e0a48
  Eric Kooistra authored 9 years ago
  
  797e0a48
Jul 15, 2015
- Explained g_link_status_check and g_pre_header_padding. · 6a100b57
  Eric Kooistra authored 9 years ago
  
  6a100b57
- Added tx_unidir_control via MM in comment. · 71914bb4
  Eric Kooistra authored 9 years ago
  
  71914bb4
- Added eplanation of link fault operation. · 7372d3df
  Eric Kooistra authored 9 years ago
  
  7372d3df
Jun 26, 2015
- Improved legenda of cs_w and cs_w_w in table. · 3f0a25a0
  Eric Kooistra authored 9 years ago
  
  3f0a25a0