Added tx_unidir_control via MM in comment.

libraries/technology/mac_10g/tb_tech_mac_10g_pkg.vhd

@@ -165,6 +165,10 @@ PACKAGE BODY tb_tech_mac_10g_pkg IS
     proc_mem_mm_bus_rd(mm_offset+16#0803#,               mm_clk, mm_miso, mm_mosi);  -- RW, rx_frame_addr1 = 0, e.g. 0x1234, for primary SRC_MAC = 12-34-56-78-9A-BC
     proc_common_wait_some_cycles(mm_clk, 10);
     
+    ---- . tx write
+    --proc_mem_mm_bus_wr(mm_offset+16#1120#,            3, mm_clk, mm_miso, mm_mosi);  -- RW, tx_unidir_control = 3 to enable unidir and disable remote fault sequence generation
+    --proc_common_wait_some_cycles(mm_clk, 10);
+    
     -- . tx read
     proc_mem_mm_bus_rd(mm_offset+16#1040#,               mm_clk, mm_miso, mm_mosi);  -- RW, tx_padins_control = 1, insert padding to ensure 64 bytes including CRC
     proc_mem_mm_bus_rd(mm_offset+16#1080#,               mm_clk, mm_miso, mm_mosi);  -- RW, tx_crcins_control = 3, compute and insert CRC
@@ -197,6 +201,7 @@ PACKAGE BODY tb_tech_mac_10g_pkg IS
                                             SIGNAL   mm_miso             : IN  t_mem_miso;
                                             SIGNAL   mm_mosi             : OUT t_mem_mosi) IS
   BEGIN
+    -- The Low Latency Ethernet 10G MAC uses legacy MAC MM interface, so the register offsets of the 10Gbps Ethernet MAC still apply
     proc_tech_mac_10g_setup_stratixiv(src_mac, mm_offset, mm_clk, mm_miso, mm_mosi);
   END proc_tech_mac_10g_setup_arria10;